• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 12 matches

• 2018
• 
  Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal:
  Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization". Int. J. Reconfigurable Comput. 2018: 6075043:1 (2018)
• 
  Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly:
  Corrigendum to "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability". Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Omar Ahmed, Shawki Areibi, Gary Gréwal:
  Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm". Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
  Reconfigurable Network Stream Processing on Virtualized FPGA Resources. Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Nitish Das, P. Aruna Priya:
  FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method. Int. J. Reconfigurable Comput. 2018: 6831901:1-6831901:15 (2018)
• 
  Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin:
  RP-Ring: A Heterogeneous Multi-FPGA Accelerator. Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Lilia Kechiche, Lamjed Touil, Bouraoui Ouni:
  Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction. Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, Huazhong Yang:
  Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL. Int. J. Reconfigurable Comput. 2018: 1785892:1-1785892:10 (2018)
• 
  Faisal Mahmood, Mart Toots, Lars-Göran Öfverstedt, Ulf Skoglund:
  Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal. Int. J. Reconfigurable Comput. 2018: 1403181:1-1403181:17 (2018)
• 
  Bruno da Silva, An Braeken, Federico Domínguez, Abdellah Touhafi:
  Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator. Int. J. Reconfigurable Comput. 2018 (2018)
• 
  Bahram N. Uchevler, Kjetil Svarstad:
  Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions. Int. J. Reconfigurable Comput. 2018: 3276159:1-3276159:25 (2018)
• 
  Ka Fai Cedric Yiu, Siow Yong Low:
  On a Real-Time Blind Signal Separation Noise Reduction System. Int. J. Reconfigurable Comput. 2018: 3721756:1-3721756:9 (2018)