- Haruhisa Tsuyama, Tsutomu Maruyama:
GPU and FPGA Acceleration of Level Set Method. SIGARCH Comput. Archit. News 42(4): 21-25 (2014) - Tao Wang, Guangyu Sun, Jiahua Chen, Jian Gong, Haoyang Wu, Xiaoguang Li, Songwu Lu, Jason Cong:
GRT: A Reconfigurable SDR Platform with High Performance and Usability. SIGARCH Comput. Archit. News 42(4): 51-56 (2014) - Tsuyoshi Watanabe, Naohito Nakasato:
GPU Accelerated Hybrid Tree Algorithm for Collision Less N-body Simulations. SIGARCH Comput. Archit. News 42(4): 15-20 (2014) - 2013
- Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41(5): 35-40 (2013) - Florent de Dinechin, Matei Istoan, Guillaume Sergent:
Fixed-point trigonometric functions on FPGAs. SIGARCH Comput. Archit. News 41(5): 83-88 (2013) - Heiner Giefers, Christian Plessl, Jens Förstner:
Accelerating finite difference time domain simulations with reconfigurable dataflow computers. SIGARCH Comput. Archit. News 41(5): 65-70 (2013) - Ivan Godard:
The Mill: split-stream encoding. SIGARCH Comput. Archit. News 41(5): 1-5 (2013) - Apala Guha, Yao Zhang, Raihan Ur Rasool
, Andrew A. Chien:
Systematic evaluation of workload clustering for extremely energy-efficient architectures. SIGARCH Comput. Archit. News 41(2): 22-29 (2013) - Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont:
Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. SIGARCH Comput. Archit. News 41(5): 59-64 (2013) - Liucheng Guo, David B. Thomas, Wayne Luk:
Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News 41(5): 101-106 (2013) - Chuan Hong, Khaled Benkrid, Mohd Nazrin Md. Isa, Xabier Iturbe:
A run-time reconfigurable system for adaptive high performance efficient computing. SIGARCH Comput. Archit. News 41(5): 113-118 (2013) - Tomislav Janjusic, Krishna M. Kavi:
Gleipnir: a memory profiling and tracing tool. SIGARCH Comput. Archit. News 41(4): 8-12 (2013) - Atabak Mahram, Martin C. Herbordt:
NCBI BLASTP on the convey HC1-EX. SIGARCH Comput. Archit. News 41(5): 41-46 (2013) - Subhashis Maitra, Amitabha Sinha:
High performance MAC unit for DSP and cryptographic applications. SIGARCH Comput. Archit. News 41(2): 47-55 (2013) - Subhashis Maitra, Amitabha Sinha:
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. SIGARCH Comput. Archit. News 41(4): 1-7 (2013) - Subhashis Maitra, Amitabha Sinha:
Design and simulation of MAC unit using combinational circuit and adder. SIGARCH Comput. Archit. News 41(5): 25-33 (2013) - Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41(5): 71-76 (2013) - Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. SIGARCH Comput. Archit. News 41(5): 77-82 (2013) - Santanu Pal, Amitabha Sinha, Pijush Biswas:
FPGA implementation of a novel DCT architecture reducing constant cosine terms. SIGARCH Comput. Archit. News 41(2): 36-40 (2013) - Gary Plumbridge, Jack Whitham, Neil C. Audsley:
Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators. SIGARCH Comput. Archit. News 41(5): 107-117 (2013) - Amrita Saha, Pijush Biswas, Amitabha Sinha:
An integrated development platform of a reconfigurable radio processor for software defined radio. SIGARCH Comput. Archit. News 41(2): 30-35 (2013) - Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha:
Performance analysis of a FPGA based novel binary and DBNS multiplier. SIGARCH Comput. Archit. News 41(2): 9-16 (2013) - Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno, Kyo Koizumi, Satoru Yamamoto:
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. SIGARCH Comput. Archit. News 41(5): 47-52 (2013) - Michael Sartin-Tarm, Tony Nowatzki, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan:
Constraint centric scheduling guide. SIGARCH Comput. Archit. News 41(2): 17-21 (2013) - Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty:
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. SIGARCH Comput. Archit. News 41(2): 1-8 (2013) - Jubee Tada:
Performance evaluation of 3-D stacked 32-bit parallel multipliers. SIGARCH Comput. Archit. News 41(5): 89-94 (2013) - Yuichiro Tanaka, Shimpei Sato, Kenji Kise:
The Ultrasmall soft processor. SIGARCH Comput. Archit. News 41(5): 95-100 (2013) - Alexander Thomasian:
Disk arrays with multiple RAID levels. SIGARCH Comput. Archit. News 41(5): 6-24 (2013) - Mark Thorson:
Internet nuggets. SIGARCH Comput. Archit. News 41(2): 56-71 (2013) - Mark Thorson:
Internet nuggets. SIGARCH Comput. Archit. News 41(4): 13-22 (2013)
