- Toshinori Sato, Itsujiro Arita:
Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN 2000: 78-87 - Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi
, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194 - Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko:
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. ISPAN 2000: 114-120 - Takayoshi Touyama, Atsuo Takahashi, Susumu Horiguchi:
Optimal Location of High-speed Facility in Heterogeneous Networks. ISPAN 2000: 246-253 - Nobuo Tsuda, Tatsuyuki Shimizu:
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement. ISPAN 2000: 24-29 - Hao Wang, Xiaoyan Xie, Zhiyong Huang:
Collaborative and Interactive Room Design on the Web. ISPAN 2000: 238-245 - Shih-Lin Wu, Chih-Yu Lin, Yu-Chee Tseng, Jang-Ping Sheu:
A New Multi-Channel MAC Protocol with On-Demand Channel Assignment for Multi-Hop Mobile Ad Hoc Networks. ISPAN 2000: 232-237 - Limin Xiang, Kazuo Ushijima:
Optimal Parallel Merging Algorithms on BSR. ISPAN 2000: 12-17 - Jipeng Zhou, Francis C. M. Lau:
Fault-Tolerant Wormhole Routing in 2D Meshes. ISPAN 2000: 94-101 - Sotirios G. Ziavras:
Versatile Processor Design for Efficiency and High Performance. ISPAN 2000: 266-273 - 5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA. IEEE Computer Society 2000, ISBN 0-7695-0936-3 [contents]
