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Noboru Tanabe
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2010 – 2019
- 2018
- [c22]Noboru Tanabe
, Toshio Endo:
Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache. HP3C 2018: 27-34 - [c21]Noboru Tanabe
, Toshio Endo:
Characterizing Memory-Latency Sensitivity of Sparse Matrix Kernels. PDP 2018: 249-254 - 2013
- [j7]Noboru Tanabe
, Atsushi Ohta:
Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism. IEICE Trans. Inf. Syst. 96-D(12): 2536-2544 (2013) - [c20]Noboru Tanabe
, Sonoko Tomimori, Masami Takata, Kazuki Joe:
Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems. ICA3PP (1) 2013: 402-415 - 2011
- [c19]Noboru Tanabe
, Yuuka Ogawa, Masami Takata, Kazuki Joe:
Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs. PDP 2011: 101-108 - [c18]Noboru Tanabe
, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe:
A memory accelerator with gather functions for bandwidth-bound irregular applications. IA3@SC 2011: 35-42 - 2010
- [j6]Noboru Tanabe
, Hirotaka Hakozaki, Hiroshi Ando, Yasunori Dohi, Zhengzhe Luo, Hironori Nakajo:
An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. J. Supercomput. 51(3): 279-309 (2010) - [c17]Noboru Tanabe
, Hironori Nakajo:
Acceleration for MPI derived datatypes using an enhancer of memory and network. IPDPS Workshops 2010: 1-6
2000 – 2009
- 2009
- [c16]Noboru Tanabe
, Atsushi Ohta, Pulung Waskito, Hironori Nakajo:
Network Interface Architecture for Scalable Message Queue Processing. ICPADS 2009: 268-275 - [c15]Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe:
The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. PDPTA 2009: 427-433 - 2008
- [c14]Noboru Tanabe
, Hironori Nakajo:
An Enhancer of Memory and Network for Cluster and its Applications. PDCAT 2008: 99-106 - [c13]Noboru Tanabe
, Hironori Nakajo:
Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. PVM/MPI 2008: 324-325 - 2007
- [j5]Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi
, Junji Yamamoto, Noboru Tanabe
, Tomohiro Kudoh, Hideharu Amano:
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distributed Syst. 18(9): 1282-1295 (2007) - [c12]Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62 - [c11]Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793 - 2006
- [c10]Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
:
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. FPL 2006: 1-4 - [c9]Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki:
Implementation of PC Cluster System with Memory Mapped File by Commodity OS. PDPTA 2006: 902-908 - 2005
- [c8]Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC 2005: 211-218 - [c7]Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe
, Hironori Nakajo:
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780 - [c6]Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467 - 2004
- [c5]Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano:
A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128 - 2002
- [j4]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5(1): 7-17 (2002) - [c4]Noboru Tanabe
, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14 - 2000
- [c3]Noboru Tanabe
, Junji Yamamoto, Hiroaki Nishi
, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16 - [c2]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi
, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194
1990 – 1999
- 1996
- [j3]Yasushi Kawakura, Noboru Tanabe
, Shigeru Oyanagi:
Improving the performance of global communication on a three-dimensional torus network. Syst. Comput. Jpn. 27(6): 24-32 (1996) - 1992
- [j2]Noboru Tanabe
, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi:
Implementation of the prodigy parallel AI machine and performance evaluation of communication. Syst. Comput. Jpn. 23(8): 1-12 (1992) - 1991
- [c1]Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi:
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. ICPP (1) 1991: 509-516
1980 – 1989
- 1989
- [j1]Takashi Suzuoka, Noboru Tanabe
, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi:
Network Performance of the Prodigy Parallel AI Machine. Syst. Comput. Jpn. 20(9): 44-51 (1989)
Coauthor Index
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