- Michal Sovcik
, Martin Kovác, Daniel Arbet, Viera Stopjaková:
Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology. DDECS 2017: 127-132 - Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Formal Design Space Exploration for memristor-based crossbar architecture. DDECS 2017: 145-150 - Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik:
A scalable technique to identify true critical paths in sequential circuits. DDECS 2017: 152-157 - Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - Michal Wolodzko, Wieslaw Kuzmicz:
A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology. DDECS 2017: 79-82 - Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui:
On the robustness of memristor based logic gates. DDECS 2017: 158-163 - Tohid Taghizad Gogjeh Yaran, Suleyman Tosun:
Improving combinational circuit resilience against soft errors via selective resource allocation. DDECS 2017: 12-15 - Manfred Dietrich, Ondrej Novák:
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017. IEEE 2017, ISBN 978-1-5386-0472-4 [contents]
