"A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration."

Aamir Zia et al. (2010)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2009.2017750

access: closed

type: Journal Article

metadata version: 2024-02-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/ZiaJKCKM10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ZiaJKCKM10
Aamir Zia, Philip Jacob, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald:
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 967-977 (2010)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.