"A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC ..."

Claudio Nani et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631522

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type: Conference or Workshop Paper

metadata version: 2024-10-17

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Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, D. Albano, C. Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, D. Burgos, Gabriele Minoia, P. Rossi, Marco Sosio, L. Vignoli, Enrico Temporiti, S. Scouten, S. Jantzi:
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. VLSI Technology and Circuits 2024: 1-2

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