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2020 – today
- 2024
[c11]Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, T. Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi:
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. VLSI Technology and Circuits 2024: 1-2- [c10]Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, D. Albano, C. Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, D. Burgos, Gabriele Minoia, P. Rossi, Marco Sosio, L. Vignoli, Enrico Temporiti, S. Scouten, S. Jantzi:
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. VLSI Technology and Circuits 2024: 1-2 - 2022
- [c9]Marco Ronchi, Francesco Malena, Michele Caselli, Devis Gatti, Ermano Picco, Elena Salurso, Marco Sosio, Lucio Ticli, Alessandro Tomasoni, Eusebio Di-Cola, Tommaso Majo, Fabio Osnato, Elio Guidetti, Andrea Boni:
An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor. ICECS 2022 2022: 1-4 - 2020
- [j8]Matteo Pisati
, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani:
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. IEEE J. Solid State Circuits 55(1): 6-18 (2020)
2010 – 2019
- 2019
- [c8]Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti:
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. ISSCC 2019: 116-118 - 2018
- [c7]Alessandro Truppi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Ronchi, Marco Sosio:
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS 2018: 1-4 - 2013
- [j7]Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Samuel Er-Shen Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello:
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. IEEE J. Solid State Circuits 48(11): 2746-2761 (2013) - [j6]Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello:
SAW-Less Analog Front-End Receivers for TDD and FDD. IEEE J. Solid State Circuits 48(12): 3067-3079 (2013) - [j5]Marco Sosio, Antonio Liscidini, Rinaldo Castello:
An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 66-70 (2013) - [c6]Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello:
SAW-less analog front-end receivers for TDD and FDD. ISSCC 2013: 82-83 - 2012
- [j4]Marco Sosio, Antonio Liscidini, Rinaldo Castello:
A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. IEEE Trans. Circuits Syst. II Express Briefs 59-II(4): 214-218 (2012) - [c5]Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello:
A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. ISSCC 2012: 162-164 - 2011
- [j3]Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto:
A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 88-97 (2011) - [c4]Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis:
A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. ESSCIRC 2011: 391-394 - 2010
- [j2]Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto:
A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers. IEEE J. Solid State Circuits 45(10): 2104-2115 (2010)
2000 – 2009
- 2009
- [c3]Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto:
A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS. ISSCC 2009: 412-413 - 2008
- [c2]Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto:
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS. ISSCC 2008: 216-217 - 2007
- [j1]Massimo Brandolini, Marco Sosio, Francesco Svelto:
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS. IEEE J. Solid State Circuits 42(6): 1310-1317 (2007) - 2006
- [c1]Massimo Brandolini, Marco Sosio, Francesco Svelto:
A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS. ISSCC 2006: 1882-1891
Coauthor Index
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last updated on 2024-10-18 20:31 CEST by the dblp team
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