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Sujan Pandey
Person information
- affiliation: University of Bremen, Germany
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Journal Articles
- 2007
- [j1]Sujan Pandey, Manfred Glesner:
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1111-1124 (2007)
Conference and Workshop Papers
- 2014
- [c17]Sujan Pandey, Bart Vermeulen:
Transient errors resiliency analysis technique for automotive safety critical applications. DATE 2014: 1-4 - 2012
- [c16]Sujan Pandey, Klaas Brink:
Soft-errors resilient logic optimization for low power. IOLTS 2012: 19-24 - 2008
- [c15]Sujan Pandey, Rolf Drechsler:
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC 2008: 601-606 - [c14]Sujan Pandey, Rolf Drechsler:
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE 2008: 206-211 - [c13]Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992 - 2007
- [c12]Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS 2007: 242-254 - [c11]Sujan Pandey, Christian Genz, Rolf Drechsler:
Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC 2007: 304-307 - 2006
- [c10]Sujan Pandey, Manfred Glesner:
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC 2006: 663-668 - [c9]Sujan Pandey, Manfred Glesner:
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL 2006: 1-6 - [c8]Sujan Pandey, Manfred Glesner:
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS 2006 - [c7]Sujan Pandey, Nurten Utlu, Manfred Glesner:
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC 2006: 222-227 - [c6]Sujan Pandey, Tudor Murgan, Manfred Glesner:
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC 2006: 296-301 - [c5]Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC 2006: 302-307 - 2005
- [c4]Sujan Pandey, Manfred Glesner, Max Mühlhäuser:
On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL 2005: 374-379 - [c3]Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser:
High level hardware/software communication estimation in shared memory architecture. ISCAS (1) 2005: 37-40 - [c2]Thomas Hollstein, Sujan Pandey, Manfred Glesner:
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC 2005: 85-92 - [c1]Sujan Pandey, Manfred Glesner, Max Mühlhäuser:
Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI 2005: 230-235
Coauthor Index
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