"Statistical on-chip communication bus synthesis and voltage scaling under ..."

Sujan Pandey, Manfred Glesner (2006)

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DOI: 10.1145/1146909.1147078

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/dac/PandeyG06
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Sujan Pandey, Manfred Glesner:
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC 2006: 663-668

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