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ORCIDYong-Seo Koo
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2020 – today
- 2024
[j19]Sang-Wook Kwon
, Kyoung-Il Do, Jeong-Min Lee, U-Yeol Seo, Yong-Seo Koo:
Design of High-Robustness LDO Regulator With Floating SCR Based ESD Protection Circuit Using High Gain Buffer. IEEE Access 12: 33555-33568 (2024)- [j18]U-Yeol Seo, Jeong-Min Lee, Sang-Wook Kwon, Yong-Seo Koo:
Design of high-reliability LDO regulator incorporated with SCR based ESD protection circuit using transient switch structure. IEICE Electron. Express 21(11): 20240097 (2024) - [c13]U-Yeol Seo, Sang-Wook Kwon, Seung Gu Jeong, Jeong-Min Lee, Kwang-Yeob Lee, Yong-Seo Koo:
Development of Diode Triggering SCR-Based ESD Protection Circuit with Improved Trigger Voltage for Low Voltage Application. ICEIC 2024: 1-3 - 2023
- [j17]Sang-Wook Kwon, Yong-Seo Koo:
Design of LDO Regulator With High Reliability ESD Protection Circuit Using Analog Current Switch Structure for 5-V Applications. IEEE Access 11: 37472-37482 (2023) - [j16]Sang-Wook Kwon, Seung Gu Jeong, Jung Min Lee, Yong-Seo Koo:
High-reliability LDO regulator with built-in SCR-based ESD protection circuit designed for effective peak voltage reduction. IEICE Electron. Express 20(17): 20230231 (2023) - [c12]Sang-Wook Kwon, Seung Gu Jeong, Kwang-Yeob Lee, Yong-Seo Koo:
Design of Low Drop Out Regulator with High Robustness ESD Protection Circuit Using Current Buffer Structure. ICEIC 2023: 1-4 - 2022
- [j15]Sang-Wook Kwon, Yong-Seo Koo:
Design of high-reliability LDO regulator with SCR based ESD protection circuit using body technique and load transient detection. IEICE Electron. Express 19(11): 20220110 (2022) - [j14]Sang-Wook Kwon, Yong-Seo Koo:
Design of capless LDO regulator with low voltage application based ESD protection circuit using SR-latch switch structure. IEICE Electron. Express 19(15): 20220221 (2022) - [c11]Jang-Han Joung, Sang-Wook Kwon, Jun-Ho Kong, Byung-Seok Lee, Yong-Seo Koo:
Study on ESD Protection Device Based on 4H-SiC GGNMOS with Improved Snapback Characteristics. ICEIC 2022: 1-3 - 2021
- [c10]Kyoung-Il Do, Seung-Hoo Jin, Byung-Seok Lee, Je-Wook Woo, Yong-Seo Koo:
Design of All-Directional ESD Protection circuit with SCR-based I/O and LIGBT-based Power clamp. ICEIC 2021: 1-3
2010 – 2019
- 2019
- [c9]Byung-Seok Lee, Hee-Guk Chae, Yong-Seo Koo, Kyeong-Il Do, Jin-Woo Eo:
2-stage ESD protection circuit with high holding voltage and low trigger voltage for high voltage applications. ICEIC 2019: 1-4 - 2018
- [c8]Kyung-Il Do, Byung-Seok Lee, Hee-Guk Chae, Jeong-Ju Seo, Yong-Seo Koo:
A New Low Trigger SCR with Latch up Immunity for 5V Application. EECS 2018: 524-527 - 2015
- [c7]Kwang-Yeob Lee, Gyutaek Kyung, Tae Ryong Park, Jae-Chang Kwak, Yong-Seo Koo:
A design of a GP-GPU based stream processor for an image processing. TSP 2015: 535-539 - 2013
- [j13]Yong-Seo Koo:
A design of low-area low drop-out regulator using body bias technique. IEICE Electron. Express 10(19): 20130300 (2013) - [j12]Jin-Woo Jung, Yong-Seo Koo, Kwang-Yeob Lee:
Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit. IEICE Electron. Express 10(20): 20130516 (2013) - [j11]Jin-Woo Jung, Yong-Seo Koo, Kwang-Yeob Lee:
Erratum: Design of high-reliability LDO with current limiting characteristics with built-in new high tolerance ESD protection circuit [IEICE Electronics Express Vol 10 (2013) No 20 pp 20130516]. IEICE Electron. Express 10(21): 20138001 (2013) - [c6]Jae-Chang Kwak, Tae Ryong Park, Yong-Seo Koo, Kwang-Yeob Lee:
Implementation of object recognition and tracking algorithm on real-time basis. EUROCON 2013: 2000-2004 - [c5]Jae-Chang Kwak, Tae Ryong Park, Yong-Seo Koo, Kwang-Yeob Lee:
Implementation of Improved Census Transform Stereo Matching on a Multicore Processor. MUE 2013: 989-995 - 2012
- [j10]Yong-Seo Koo, Kwang-Yeob Lee:
SCR-based ESD protection device with low trigger and high robustness for I/O clamp. IEICE Electron. Express 9(3): 200-205 (2012) - [j9]Yong-Seo Koo:
Electrical characteristics of novel SCR - based ESD protection for power clamp. IEICE Electron. Express 9(18): 1479-1484 (2012) - [c4]Jung-yong Lee, Hoon Heo, Kwang-Yeob Lee, Yong-Seo Koo:
Design of multi-core rasterizer for parallel processing. ISOCC 2012: 494-497 - 2011
- [j8]Yong-Seo Koo:
Analysis of the electrical characteristics of SCR-based ESD Protection Device (PTSCR) in 0.13/0.18/0.35um process technology. IEICE Electron. Express 8(1): 8-12 (2011) - [j7]Yong-Seo Koo:
Electrical characteristics and thermal reliability of BJT-inserted GSTNMOS using the 65nm CMOS process. IEICE Electron. Express 8(5): 259-265 (2011) - [j6]Jong-Il Won, Jin-Woo Jung, Yong-Seo Koo:
SCR stacking structure with high holding voltage for high voltage power clamp. IEICE Electron. Express 8(16): 1260-1266 (2011) - [c3]Yong-Seo Koo, Kwang-Yeob Lee, Joong-Ho Choi, Chan-Ho Lee, Yoon-Sik Lee, Yil-Suk Yang:
Electrical characteristics of novel ESD protection devices for I/O and power clamp. ISCAS 2011: 937-940
2000 – 2009
- 2009
- [j5]Yong-Seo Koo, Kwi-Dong Kim, Jong-Kee Kwon:
ESD protection circuit with low triggering voltage and fast turn-on using substrate-triggered technique. IEICE Electron. Express 6(8): 467-471 (2009) - [j4]Yong-Seo Koo:
Design of SCR-Based ESD Protection Device for Power Clamp Using Deep-Submicron CMOS Technology. IEICE Trans. Electron. 92-C(9): 1188-1193 (2009) - [j3]Yong-Seo Koo, Kwang-Yeob Lee, Kui-Dong Kim, Jong-Ki Kwon:
Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology. Microelectron. J. 40(6): 1007-1012 (2009) - [c2]Jong-Il Won, Samuell Shin, Ka-San Ha, Jong-Ki Kwon, Yong-Seo Koo:
The Novel SCR-based ESD Protection Device with High Holding Voltage. ISCAS 2009: 1779-1782 - [c1]Kwang-Yeob Lee, Tae-Ryoung Park, Jae-Chang Kwak, Yong-Seo Koo:
A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture. MMEDIA 2009: 121-124 - 2008
- [j2]Yong-Seo Koo, Kwang-Yeob Lee, Kui-Dong Kim, Jong-Ki Kwon:
The design of high holding voltage SCR for whole-chip ESD protection. IEICE Electron. Express 5(17): 624-630 (2008) - 2007
- [j1]Yong-Seo Koo:
Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature. Microelectron. J. 38(10-11): 1027-1033 (2007)
Coauthor Index
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