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ORCIDJeong-Sup Lee
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2010 – 2019
- 2017
[j4]Taehun Yoon
, Joon-Yeong Lee, Jinhee Lee, Kwangseok Han, Jeong-Sup Lee, Sangeun Lee, Taeho Kim, Jinho Han, Hyosup Won, Jinho Park, Hyeon-Min Bae:
A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links. IEEE J. Solid State Circuits 52(3): 688-703 (2017)- 2016
- [j3]Joon-Yeong Lee, Kwangseok Han, Taehun Yoon, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Jinho Park, Hyeon-Min Bae:
A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation. IEEE J. Solid State Circuits 51(10): 2475-2484 (2016) - 2015
- [j2]Hyosup Won, Taehun Yoon, Jinho Han, Joon-Yeong Lee, Jong-Hyeok Yoon, Taeho Kim, Jeong-Sup Lee, Sangeun Lee, Kwangseok Han, Jinhee Lee, Jinho Park, Hyeon-Min Bae:
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. IEEE J. Solid State Circuits 50(2): 399-413 (2015) - [j1]Soon-Won Kwon, Joon-Yeong Lee, Jinhee Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Hyosup Won, Jinho Park, Hyeon-Min Bae:
An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2817-2828 (2015) - [c3]Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae:
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation. CICC 2015: 1-4 - [c2]Taehun Yoon, Joon-Yeong Lee, Kwangseok Han, Jeong-Sup Lee, Sangeun Lee, Taeho Kim, Hyosup Won, Jinho Park, Hyeon-Min Bae:
A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards. VLSIC 2015: 212-
2000 – 2009
- 2008
- [c1]Jeong-Sup Lee, In-Cheol Park:
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS 2008: 236-239
Coauthor Index
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