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ORCIDZhenyu Sun 0001
Person information
- affiliation: Broadcom Corporation, Irvine, CA, USA
Other persons with the same name
- Zhenyu Sun — disambiguation page
- Zhenyu Sun 0002 — Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
- Zhenyu Sun 0003 — National University of Singapore, Singapore (and 1 more)
- Zhenyu Sun 0004 — Simulation Technology and Service CO., Ltd AVIC International, Shanghai, China
- Zhenyu Sun 0005 — Neural Galaxy, Beijing, China
- Zhenyu Sun 0006
![[0000-0002-1177-1797]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-1177-1797")
— Southeast University, Nanjing, China - Zhenyu Sun 0007 — Xiamen University, Xiamen, China
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Journal Articles
- 2016
[j6]Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li:
Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 212-221 (2016)- [j5]Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li:
Array Organization and Data Management Exploration in Racetrack Memory. IEEE Trans. Computers 65(4): 1041-1054 (2016) - 2015
- [j4]Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones:
Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1170-1174 (2015) - 2014
- [j3]Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu:
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1281-1293 (2014) - 2012
- [j2]Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen:
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. ACM J. Emerg. Technol. Comput. Syst. 8(2): 13:1-13:16 (2012) - [j1]Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang:
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2020-2030 (2012)
Conference and Workshop Papers
- 2015
- [c9]Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun:
The evolutionary spintronic technologies and their usage in high performance computing. SoCC 2015: 350-355 - 2014
- [c8]Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615 - [c7]Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li:
Design exploration of racetrack lower-level caches. ISLPED 2014: 263-266 - 2013
- [c6]Zhenyu Sun, Wenqing Wu, Hai (Helen) Li:
Cross-layer racetrack memory design for ultra high density and low power consumption. DAC 2013: 53:1-53:6 - 2012
- [c5]Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu:
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD 2012: 88-94 - [c4]Zhenyu Sun, Hai Li, Wenqing Wu:
A dual-mode architecture for fast-switching STT-RAM. ISLPED 2012: 45-50 - [c3]Zhenyu Sun, Xiuyuan Bi, Hai Li:
Process variation aware data management for STT-RAM cache design. ISLPED 2012: 179-184 - 2011
- [c2]Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu:
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338 - 2010
- [c1]Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang:
Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. ICCAD 2010: 432-437
Coauthor Index
aka: Hai (Helen) Li
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