"A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory ..."

Jianxing Wang et al. (2014)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.2014.6742958

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aspdac/WangTWOSL14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/WangTWOSL14
Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.