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2020 – today
- 2021
[j4]Xiaoxiao Liu
, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen:
Exploring Applications of STT-RAM in GPU Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 238-249 (2021)
2010 – 2019
- 2017
- [j3]Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li:
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1807-1820 (2017) - 2016
- [j2]Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li:
Array Organization and Data Management Exploration in Racetrack Memory. IEEE Trans. Computers 65(4): 1041-1054 (2016) - [c13]Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu:
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. ISLPED 2016: 4-9 - 2015
- [c12]Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen:
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC 2015: 490-495 - [c11]Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun:
The evolutionary spintronic technologies and their usage in high performance computing. SoCC 2015: 350-355 - 2014
- [j1]Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu:
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1281-1293 (2014) - [c10]Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li:
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. ICCD 2014: 133-138 - [c9]Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li:
Design exploration of racetrack lower-level caches. ISLPED 2014: 263-266 - 2013
- [c8]Xiuyuan Bi, Mohamed Anis Weldon, Hai Li:
STT-RAM designs supporting dual-port accesses. DATE 2013: 853-858 - [c7]Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li:
Unleashing the potential of MLC STT-RAM caches. ICCAD 2013: 429-436 - [c6]Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li:
A pseudo-weighted sensing scheme for memristor based cross-point memory. NANOARCH 2013: 38-39 - 2012
- [c5]Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino:
Spintronic memristor based temperature sensor design with CMOS current reference. DATE 2012: 1301-1306 - [c4]Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu:
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD 2012: 88-94 - [c3]Zhenyu Sun, Xiuyuan Bi, Hai Li:
Process variation aware data management for STT-RAM cache design. ISLPED 2012: 179-184 - [c2]Xiuyuan Bi, Hai Li, Jae-Joon Kim:
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI 2012: 374-379 - 2011
- [c1]Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu:
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338
Coauthor Index
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