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Jaehyun Park 0014
Person information
- affiliation: Yonsei University, School of Electrical and Electronics Engineering, Seoul, Korea
- affiliation: Kwangwoon University, Department of Electronic Engineering, Seoul, Korea
Other persons with the same name
- Jaehyun Park (aka: Jae Hyun Park) — disambiguation page
- Jaehyun Park 0001 — Pukyong National University, Department of Electronic Engineering, Busan, South Korea (and 3 more)
- Jaehyun Park 0002 — Korea Advanced Institute of Science and Technology, School of Computing, Graduate School of Information Security, Daejeon, South Korea
- Jaehyun Park 0003 — Inha University, Department of Information and Communication Engineering, Incheon, South Korea
- Jaehyun Park 0004 — Incheon National University, South Korea
- Jaehyun Park 0005 — University of Ulsan, Department of Electrical, Electronic and Computer Engineering, Korea (and 3 more)
- Jaehyun Park 0006 — Seoul National University, Department of Intelligence and Information, Korea
- Jaehyun Park 0007 (aka: Jae Hyun Park 0007) — Hong Kong Polytechnic University, School of Design, Hong Kong (and 3 more)
- Jaehyun Park 0008 — Pusan National University, Department of Electrical Engineering, Busan, Korea
- Jaehyun Park 0009 — Stanford University, USA
- Jae Hyun Park 0010 (aka: Jaehyun Park 0010) — University of California, San Diego, USA
- Jaehyun Park 0011 — Hanyang University, Department of Automotive Engineering, Seoul, Korea
- Jaehyun Park 0012 (aka: Jae Hyun Park 0012) — Sungkyunkwan University, Department of Artificial Intelligence, AI, Korea
- Jaehyun Park 0013 — Yeungnam University, Department of Computer Engineering, Gyeongsan, Korea
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Journal Articles
- 2023
- [j2]Jaehyun Park, Sangheon Lee, Hanwool Jeong:
Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 797-805 (2023) - [j1]Sangheon Lee, Jaehyun Park, Hanwool Jeong:
Cross-Coupled nFET Preamplifier for Low Voltage SRAM. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3604-3608 (2023)
Conference and Workshop Papers
- 2024
- [c1]Giseok Kim, Jaehyun Park, Seong-Ook Jung:
Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization. ICEIC 2024: 1-3
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last updated on 2024-12-26 01:54 CET by the dblp team
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