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ORCIDShin-ichi O'Uchi
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2020 – today
- 2022
[c14]Shin-ichi O'Uchi, Ryusuke Hayashi:
Short Floating-Point CNN Accelerator for Brain-Computer Interface to Decode Visual Information. ISCAS 2022: 2299-2303- [c13]Xinpei Zhang, Yi Ding, Mingfei Yu, Shin-ichi O'Uchi, Masahiro Fujita:
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. ISQED 2022: 1-6
2010 – 2019
- 2019
- [c12]Wakana Nogami, Tsutomu Ikegami, Shin-ichi O'Uchi, Ryousei Takano, Tomohiro Kudoh:
Optimizing Weight Value Quantization for CNN Inference. IJCNN 2019: 1-8 - [i1]Yuma Kishi, Tsutomu Ikegami, Shin-ichi O'Uchi, Ryousei Takano, Wakana Nogami, Tomohiro Kudoh:
Perturbative GAN: GAN with Perturbation Layers. CoRR abs/1902.01514 (2019) - 2018
- [c11]Shin-ichi O'Uchi, Hiroshi Fuketa, Tsutomu Ikegami, Wakana Nogami, Takashi Matsukawa, Tomohiro Kudoh, Ryousei Takano:
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. ISCAS 2018: 1-5 - 2017
- [j8]Hiroshi Fuketa
, Shin-ichi O'Uchi, Takashi Matsukawa:
Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 392-396 (2017) - [j7]Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa:
A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1027-1031 (2017) - [j6]Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa:
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2007-2016 (2017) - 2015
- [c10]Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shin-ichi O'Uchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara:
PBTI for N-type tunnel FinFETs. ICICDT 2015: 1-4 - 2014
- [j5]Yasushi Igarashi, Tadashi Chiba, Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto:
SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 741-748 (2014) - [c9]Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O'Uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota:
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance. ESSDERC 2014: 182-185 - [c8]Shinji Migita, Takashi Matsukawa, Takahiro Mori, Koichi Fukuda, Yukinori Morita, Wataru Mizubayashi, Kazuhiko Endo, Yongxun Liu, Shin-ichi O'Uchi, Meishoku Masahara, Hiroyuki Ota:
Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration. ESSDERC 2014: 278-281 - 2013
- [j4]Kazuhiko Endo, Shin-ichi O'Uchi, Takashi Matsukawa, Yongxun Liu, Meishoku Masahara:
Independent-Double-Gate FinFET SRAM Technology. IEICE Trans. Electron. 96-C(4): 413-423 (2013) - [c7]Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O'Uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota:
Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations. ESSDERC 2013: 45-48 - [c6]Wataru Mizubayashi, Koichi Fukuda, Takahiro Mori, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Shin-ichi O'Uchi, Yuki Ishikawa, Shinji Migita, Yukinori Morita, Akihito Tanabe, Junichi Tsukada, Hiromi Yamauchi, Meishoku Masahara, Hiroyuki Ota:
Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes. ESSDERC 2013: 202-205 - 2012
- [j3]Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. IEICE Trans. Electron. 95-C(4): 686-695 (2012) - [j2]Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro:
High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. 95-C(4): 752-760 (2012) - 2010
- [c5]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. CICC 2010: 1-4 - [c4]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. ESSCIRC 2010: 474-477
2000 – 2009
- 2008
- [j1]Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Trans. Electron. 91-C(4): 534-542 (2008) - 2007
- [c3]Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. CICC 2007: 33-36 - 2006
- [c2]Nobuhiro Gemma, Shin-ichi O'Uchi, Hideyuki Funaki, Jun Okada, Sadato Hongo:
CMOS Integrated DNA Chip for Quantitative DNA Analysis. ISSCC 2006: 2288-2297 - 2002
- [c1]Shin-ichi O'Uchi, Minoru Fujishima, Koichiro Hoh:
An 8-qubit quantum-circuit processor. ISCAS (5) 2002: 209-212
Coauthor Index
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