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2020 – today
- 2022
[j9]Yu-Liang Chou
, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim Jorge:
Counterfactuals and causability in explainable artificial intelligence: Theory, algorithms, and applications. Inf. Fusion 81: 59-83 (2022)- [i3]Yu-Liang Chou, Chihcheng Hsieh, Catarina Moreira, Chun Ouyang, Joaquim Jorge, João Madeiras Pereira:
Benchmark Evaluation of Counterfactual Algorithms for XAI: From a White Box to a Black Box. CoRR abs/2203.02399 (2022) - 2021
- [j8]Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza:
LINDA-BN: An interpretable probabilistic approach for demystifying black-box predictive models. Decis. Support Syst. 150: 113561 (2021) - [i2]Yu-Liang Chou, Catarina Moreira, Peter Bruza, Chun Ouyang, Joaquim Jorge:
Counterfactuals and Causability in Explainable Artificial Intelligence: Theory, Algorithms, and Applications. CoRR abs/2103.04244 (2021) - 2020
- [i1]Catarina Moreira, Yu-Liang Chou, Mythreyi Velmurugan, Chun Ouyang, Renuka Sindhgatta, Peter Bruza:
An Interpretable Probabilistic Approach for Demystifying Black-box Predictive Models. CoRR abs/2007.10668 (2020)
2010 – 2019
- 2014
- [j7]Yu-Liang Chou, Shaoshan Liu, Eui-Young Chung, Jean-Luc Gaudiot:
An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC. IEEE Comput. Archit. Lett. 13(1): 13-16 (2014) - 2013
- [j6]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu:
A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. 39(4): 1129-1141 (2013) - [j5]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou:
A hyperscalar dual-core architecture for embedded systems. Microprocess. Microsystems 37(8-B): 929-940 (2013) - [c6]Jie Tang, Chen Liu, Yu-Liang Chou, Shaoshan Liu:
OCP: Offload Co-Processor for energy efficiency in embedded mobile systems. ASAP 2013: 107-110 - 2011
- [j4]Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen, Ding-Siang Su:
A Unitable Computing Architecture for Chip Multiprocessors. Comput. J. 54(12): 2033-2052 (2011) - 2010
- [j3]Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin:
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. 26(4): 1273-1288 (2010) - [j2]Jih-Ching Chiu, Yu-Liang Chou:
A multi-streaming SIMD multimedia computing engine. Microprocess. Microsystems 34(7-8): 247-258 (2010) - [c5]Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su:
A hyperscalar multi-core architecture. Conf. Computing Frontiers 2010: 77-78 - [c4]Jih-Ching Chiu, Yu-Liang Chou, Po-Kai Chen:
Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. ICPP 2010: 277-286
2000 – 2009
- 2009
- [c3]Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng:
A multi-streaming SIMD architecture for multimedia applications. Conf. Computing Frontiers 2009: 51-60 - [c2]Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou:
Design of a novel SIMD architecture by fusing operations and registers. ICS 2009: 503-504 - 2008
- [j1]Jih-Ching Chiu, Yu-Liang Chou, Ren-Bang Lin:
The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. J. Inf. Sci. Eng. 24(3): 965-979 (2008) - [c1]Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin:
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC 2008: 1-8
Coauthor Index
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