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ORCIDMicroprocessors and Microsystems - Embedded Hardware Design, Volume 34
Volume 34, Number 1, February 2010
- Young-Su Kwon, Nak-Woong Eum:
Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor. 1-13 - Loïc Siéler
, Camel Tanougast, Ahmed Bouridane:
A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features. 14-24 - Dariusz Kania, Adam Milik:
Logic synthesis based on decomposition for CPLDs. 25-38 - Dawid Zydek, Henry Selvaraj:
Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors. 39-48 - Yung-Yuan Chen, Kuen-Long Leu:
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. 49-61
Volume 34, Numbers 2-4, March - June 2010
- Gioacchino Fertitta, Antonio Di Stefano, Giuseppe Fiscelli, Giuseppe Costantino Giaconia:
A low power and high resolution data logger for submarine seismic monitoring. 63-72 - Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos:
A task graph execution manager for reconfigurable multi-tasking systems. 73-83 - Gul N. Khan, Victor Dumitriu:
A modeling tool for simulating and design of on-chip network systems. 84-95 - Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee:
Architectural design and FPGA implementation of radix-4 CORDIC processor. 96-101 - Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, Tae-Jin Kim, Sung-Bae Park:
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC). 102-116
Volume 34, Number 5, August 2010
- Peeter Ellervee, Gert Jervan:
Guest Editorial. 117 - Liang Guang, Ethiopia Nigussie, Jouni Isoaho, Pekka Rantala, Hannu Tenhunen:
Interconnection alternatives for hierarchical monitoring communication in parallel SoCs. 118-128 - Matthias Kamuf, Joachim Neves Rodrigues, John B. Anderson, Viktor Öwall:
Design and measurement of a variable-rate Viterbi decoder in 130-nm digital CMOS. 129-137 - Volker Gierenz, Christian Panis, Jari Nurmi:
Parameterized MAC unit generation for a scalable embedded DSP core. 138-150 - Levent Aksoy, Ece Olcay Günes, Paulo F. Flores:
Search algorithms for the multiple constant multiplications problem: Exact and approximate. 151-162
Volume 34, Number 6, October 2010
- Ahmad Patooghy, Seyed Ghassem Miremadi:
Complement routing: A methodology to design reliable routing algorithm for Network on Chips. 163-173 - W. Kurdthongmee:
Utilization of a fast MSE calculation approach to improve the image quality and accelerate the operation of a hardware K-SOM quantizer. 174-181 - Sungwoo Tak, Taehoon Kim, E. K. Park:
Integrating real-time inter-task communication channels into hardware-software codesign. 182-199 - Ismail Kadayif, Hande Sen, Selcuk Koyuncu:
Modeling soft errors for data caches and alleviating their effects on data reliability. 200-214 - Nadav Levison, Shlomo Weiss:
Branch target buffer design for embedded processors. 215-227 - Yu Zhang, Dongdong Chen, Younhee Choi, Li Chen, Seok-Bum Ko:
A high performance ECC hardware implementation with instruction-level parallelism over GF(2163). 228-236 - Wen-Jyi Hwang, Chih-Chieh Hsu, Hui-Ya Li, Sheng-Kai Weng, Tsung-Yi Yu:
High speed c-means clustering in reconfigurable hardware. 237-246
Volume 34, Numbers 7-8, November 2010
- Jih-Ching Chiu, Yu-Liang Chou:
A multi-streaming SIMD multimedia computing engine. 247-258 - Christos Georgoulas, Ioannis Andreadis:
FPGA based disparity map computation with vergence control. 259-273 - Jwu-Sheng Hu, Ming-Tang Lee, Chia-Hsing Yang:
An embedded audio-visual tracking and speech purification system on a dual-core processor platform. 274-284 - Ioakeim G. Georgoudas, P. Kyriakos, Georgios Ch. Sirakoulis, Ioannis Andreadis:
An FPGA implemented cellular automaton crowd evacuation model inspired by the electrostatic-induced potential fields. 285-300 - George Kornaros, Theofanis Orphanoudakis:
Design and implementation of high-speed buffered crossbars with efficient load balancing for multi-core SoCs. 301-315 - Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera:
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. 316-328
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