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2020 – today
- 2024
[c9]Shoichi Kabuyanagi, Takamasa Hamai, Masayuki Murase, Takeru Maeda, Masumi Saitoh, Shosuke Fujii:
A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ΔIon> 2µA/cell for 3D Stackable 4F2 High Speed Memory. VLSI Technology and Circuits 2024: 1-2- 2023
- [c8]Takamasa Hamai
, Kunifumi Suzuki, Reika Ichihara, Yusuke Higashi, Yoko Yoshimura, Kiwamu Sakuma, Kensuke Ota, Kota Takahashi, Kazuhiro Matsuo, Shosuke Fujii, Masumi Saitoh:
Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics. IRPS 2023: 1-5 - [c7]Harumi Seki, Reika Ichihara, Yusuke Higashi, Yasushi Nakasaki, Masumi Saitoh, Masamichi Suzuki:
Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V. IRPS 2023: 1-7 - 2020
- [c6]Marina Yamaguchi, Shosuke Fujii, Kensuke Ota, Masumi Saitoh:
Breakdown Lifetime Analysis of HfO2-based Ferroelectric Tunnel Junction (FTJ) Memory for In-Memory Reinforcement Learning. IRPS 2020: 1-6
2010 – 2019
- 2019
- [c5]Shosuke Fujii, Reika Ichihara, Takuya Konno, Marina Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Yoko Yoshimura, Masumi Saitoh, Masato Koyama:
Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication. VLSI Circuits 2019: 188- - 2018
- [c4]Masumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta:
Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI. ESSDERC 2018: 138-141 - [c3]Yoko Yoshimura, Kensuke Ota, Masumi Saitoh:
Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor. IRPS 2018: 5 - [c2]Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Shoichi Kabuyanagi, Tsunehiro Ino, Yasushi Nakasaki, Riichiro Takaishi, Reika Ichihara, Masumi Saitoh:
Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory. IRPS 2018: 6 - 2016
- [j2]Chika Tanaka, Masumi Saitoh, Kensuke Ota, Takayuki Ishikawa, Toshinori Numata:
BSIM4 parameter extraction for tri-gate Si nanowire transistors. Microelectron. J. 47: 1-6 (2016) - 2015
- [c1]Chika Tanaka, Keiji Ikeda, Masumi Saitoh:
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. ESSDERC 2015: 258-261
2000 – 2009
- 2006
- [j1]Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui:
Emerging nanoscale silicon devices taking advantage of nanostructure physics. IBM J. Res. Dev. 50(4-5): 411-418 (2006)
Coauthor Index
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