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ORCIDAntonin Hermanek
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2010 – 2019
- 2011
[c11]Jan Kloub, Tomas Mazanec, Antonin Hermanek:
Heterogeneous Platform for Stream Based Applications on FPGAs. FPL 2011: 401-404- 2010
- [c10]Tomas Mazanec, Antonin Hermanek, Jan Kamenický:
Blind image deconvolution algorithm on NVIDIA CUDA platform. DDECS 2010: 125-126 - [c9]Antonin Hermanek, Michal Kunes, Milan Tichý:
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. FPL 2010: 336-339
2000 – 2009
- 2008
- [j2]John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop:
The European Logarithmic Microprocesor. IEEE Trans. Computers 57(4): 532-546 (2008) - 2007
- [j1]Premysl Sucha, Zdenek Hanzálek
, Antonin Hermanek, Jan Schier:
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. J. VLSI Signal Process. 46(1): 35-53 (2007) - 2006
- [c8]Antonin Hermanek, Michal Kunes, Michal Kvasnicka:
Using Reconfigurable HW for High Dimensional CAF Computation. FPL 2006: 1-4 - [c7]Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier:
Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm. IES 2006: 1-10 - [c6]Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier:
Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm. IES 2006: 1-10 - 2004
- [c5]Antonin Hermanek, Jan Schier, Phillip A. Regalia:
Architecture design for FPGA implementation of finite interval CMA. EUSIPCO 2004: 2039-2042 - [c4]Jan Schier, Antonin Hermanek:
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. FPL 2004: 1149-1151 - 2003
- [c3]Antonin Hermanek, Zdenek Pohl, Jiri Kadlec:
FPGA Implementation of the Adpaptive Lattice Filter. FPL 2003: 1095-1098 - [c2]Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec:
Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. IPDPS 2003: 190 - 2001
- [c1]Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony D. Fagan:
Implementation of (Normalised) RLS Lattice on Virtex. FPL 2001: 91-100
Coauthor Index
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