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ORCIDMihir R. Choudhury
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Journal Articles
- 2016
[j6]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 820-831 (2016)- 2014
- [j5]Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram:
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers 63(2): 497-509 (2014) - [j4]Subhendu Roy
, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1517-1530 (2014) - 2013
- [j3]Mihir R. Choudhury, Kartik Mohanram:
Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1163-1176 (2013) - 2009
- [j2]Mihir R. Choudhury, Quming Zhou, Kartik Mohanram:
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. 25(2-3): 197-207 (2009) - [j1]Mihir R. Choudhury, Kartik Mohanram:
Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 392-405 (2009)
Conference and Workshop Papers
- 2021
- [c19]Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Shyam Ramji, Ulrich Finkler, Susan Malaika, Frederick Reiss:
CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. NeurIPS Datasets and Benchmarks 2021 - 2015
- [c18]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC 2015: 249-254 - 2014
- [c17]Ruchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler:
Bridging high performance and low power in processor design. ISLPED 2014: 183-188 - 2013
- [c16]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC 2013: 48:1-48:8 - 2011
- [c15]Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram:
Reliability-driven don't care assignment for logic synthesis. DATE 2011: 1560-1565 - 2010
- [c14]Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
Analytical model for TDDB-based performance degradation in combinational logic. DATE 2010: 423-428 - [c13]Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
TIMBER: Time borrowing and error relaying for online timing error resilience. DATE 2010: 1554-1559 - [c12]Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram:
Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI 2010: 173-178 - [c11]Mihir R. Choudhury, Kartik Mohanram:
Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD 2010: 586-591 - 2009
- [c10]Mihir R. Choudhury, Kartik Mohanram:
Timing-driven optimization using lookahead logic circuits. DAC 2009: 390-395 - [c9]Mihir R. Choudhury, Kartik Mohanram:
Masking timing errors on speed-paths in logic circuits. DATE 2009: 87-92 - 2008
- [c8]Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram:
Technology exploration for graphene nanoribbon FETs. DAC 2008: 272-277 - [c7]Mihir R. Choudhury, Kartik Mohanram:
Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE 2008: 903-908 - [c6]Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS 2008: 179-184 - 2007
- [c5]Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram:
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE 2007: 1072-1077 - [c4]Mihir R. Choudhury, Kartik Mohanram:
Accurate and scalable reliability analysis of logic circuits. DATE 2007: 1454-1459 - 2006
- [c3]Mihir R. Choudhury, Quming Zhou, Kartik Mohanram:
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD 2006: 204-209 - [c2]Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Design Optimization for Robustness to Single Event Upsets. VTS 2006: 202-207 - 2005
- [c1]Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar:
Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. VLSI Design 2005: 742-747
Informal and Other Publications
- 2021
- [i2]Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Ulrich Finkler:
Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. CoRR abs/2105.12655 (2021) - 2019
- [i1]Atin Sood, Benjamin Elder, Benjamin Herta, Chao Xue, Costas Bekas, A. Cristiano I. Malossi, Debashish Saha, Florian Scheidegger, Ganesh Venkataraman, Gegi Thomas, Giovanni Mariani, Hendrik Strobelt, Horst Samulowitz, Martin Wistuba, Matteo Manica, Mihir R. Choudhury, Rong Yan, Roxana Istrate, Ruchir Puri, Tejaswini Pedapati:
NeuNetS: An Automated Synthesis Engine for Neural Network Design. CoRR abs/1901.06261 (2019)
Coauthor Index
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