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ORCIDMadhura Purnaprajna
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Books and Theses
- 2010
[b1]Madhura Purnaprajna:
Run-time reconfigurable multiprocessors. University of Paderborn, 2010, ISBN 978-3-939350-92-7, pp. 1-170
Journal Articles
- 2023
- [j9]Srinivasan Subramaniyan
, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna:
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders. IEEE Des. Test 40(1): 85-95 (2023) - 2022
- [j8]Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthalaa, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão:
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. IEEE Commun. Surv. Tutorials 24(1): 524-556 (2022) - 2021
- [j7]Sagar Eetha, Sruthi P. K., Vibha Panty, Sahu Sai Vikram, Mihir Mody, Madhura Purnaprajna:
TileNET: Hardware accelerator for ternary Convolutional Neural Networks. Microprocess. Microsystems 83: 104039 (2021) - 2020
- [j6]Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin:
Recurrent Neural Networks: An Embedded Computing Perspective. IEEE Access 8: 57967-57996 (2020) - 2015
- [j5]Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14(2): 33:1-33:23 (2015) - 2012
- [j4]Madhura Purnaprajna, Paolo Ienne:
Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. 8(4): 33:1-33:16 (2012) - 2010
- [j3]Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert, Michael Hussmann, Michael Thies, Uwe Kastens:
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. ACM Trans. Reconfigurable Technol. Syst. 3(3): 17:1-17:25 (2010) - 2009
- [j2]Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert:
Run-time reconfigurability in embedded multiprocessors. SIGARCH Comput. Archit. News 37(2): 30-37 (2009) - 2007
- [j1]Madhura Purnaprajna, Marek Z. Reformat, Witold Pedrycz:
Genetic algorithms for hardware-software partitioning and optimal resource allocation. J. Syst. Archit. 53(7): 339-354 (2007)
Conference and Workshop Papers
- 2022
- [c17]M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna:
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. VLSID 2022: 102-107 - 2021
- [c16]Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna:
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. VLSID 2021: 240-245 - 2020
- [c15]Oscar Ferraz, Srinivasan Subramaniyan, Guohui Wang, Joseph R. Cavallaro, Gabriel Falcão, Madhura Purnaprajna:
Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications. FCCM 2020: 226 - [c14]Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna:
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs. SiPS 2020: 1-6 - 2019
- [c13]Simmi M. Bose, Varsha S. Lalapura, S. Saravanan, Madhura Purnaprajna:
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics. VLSID 2019: 347-352 - 2018
- [c12]Vanishree K, Madhura Purnaprajna:
Performance modeling for data distribution in heterogeneous computing systems: work in progress. CASES 2018: 9:1-9:3 - [c11]Nesma M. Rezk, Madhura Purnaprajna, Zain Ul-Abdin:
Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures. IPDPS Workshops 2018: 867-876 - [c10]Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna:
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. VLSID 2018: 461-462 - 2015
- [c9]Meena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan:
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. FPL 2015: 1-8 - 2013
- [c8]Madhura Purnaprajna, Paolo Ienne:
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM 2013: 53-56 - [c7]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA 2013: 279 - [c6]Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne:
Shadow And-Inverter Cones. FPL 2013: 1-4 - 2012
- [c5]Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne:
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM 2012: 224-231 - 2009
- [c4]Mario Porrmann, Madhura Purnaprajna, Christoph Puttmann:
Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. AHS 2009: 467-473 - [c3]Madhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rückert:
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. ERSA 2009: 119-125 - 2008
- [c2]Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann:
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. DATE 2008: 1462-1467 - 2004
- [c1]Madhura Purnaprajna, Marek Z. Reformat, Witold Pedrycz:
Genetic Algorithms in Hardware-Software Partitioning. ERSA 2004: 123-129
Informal and Other Publications
- 2019
- [i1]Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin:
Recurrent Neural Networks: An Embedded Computing Perspective. CoRR abs/1908.07062 (2019)
Coauthor Index
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