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Mititada Morisue
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Journal Articles
- 2003
- [j5]Hisato Fujisaka, Yuji Hidaka, Singo Kajita, Mititada Morisue:
Piecewise Linear Operators on Sigma-Delta Modulated Signals and Their Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1249-1255 (2003) - 2002
- [j4]Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue:
Bit-Stream Signal Processing Circuits and Their Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 853-860 (2002) - [j3]Takeshi Kamio, Hisato Fujisaka, Mititada Morisue:
Associative Memories Using Interaction between Multilayer Perceptrons and Sparsely Interconnected Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1220-1228 (2002) - [j2]Masahiro Sakamoto, Daisuke Hamano, Mititada Morisue:
Design of a multiple-operand redundant binary adder. Syst. Comput. Jpn. 33(10): 1-9 (2002) - 1997
- [j1]Mititada Morisue, Masayuki Yamadaya, Hiroshi Noguchi, Akinori Kanasugi:
A digital application of chaotic oscillation modes in Josephson circuit. Int. J. Intell. Syst. 12(4): 267-290 (1997)
Conference and Workshop Papers
- 2003
- [c10]Daisuke Hamano, Nobuhiro Tabuki, Hisato Fujisaka, Mititada Morisue:
Binary and multi-valued cellular array models of linear distributed parameter systems. ICECS 2003: 164-167 - 2002
- [c9]Yuji Hidaka, Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue:
Piecewise linear operations on sigma-delta modulated signals. ICECS 2002: 983-986 - 2001
- [c8]Hisato Fujisaka, Maki Akita, Mititada Morisue:
Dynamical intelligent network based on group representation theory. ICECS 2001: 79-82 - [c7]Osamu Yamagata, Nobuhiro Kataoka, Kazuhiko Tsuda, Mititada Morisue:
Method of Visualizing Homepages Using Certain Quantifiers and Its Verification. ICOIN 2001: 137-144 - 2000
- [c6]Takeshi Kamio, Shinichiro Tanaka, Mititada Morisue:
Backpropagation Algorithm for Logic Oriented Neural Networks. IJCNN (2) 2000: 123-128 - [c5]Kazuhiko Tsuda, Osamu Yamagata, Mititada Morisue:
Shopping-chances in Web-pages discovered from user's access logs. KES 2000: 800-803 - 1999
- [c4]Hisato Fujisaka, Naoyuki Masuda, Masahiro Sakamoto, Mititada Morisue:
Arithmetic circuits for single-bit digital signal processing. ICECS 1999: 1389-1392 - 1998
- [c3]Mititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto:
A Josephson Ternary Memory Circuit. ISMVL 1998: 19-24 - [c2]Ali Massoud Haidar, Mititada Morisue:
Multiple-Valued Logic Oriented Neural Networks. NC 1998: 979-982 - 1992
- [c1]Mititada Morisue, Fu-Qiang Li:
A Superconducting Ternary Systolic Array Processor. ISMVL 1992: 10-17
Coauthor Index
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