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2020 – today
- 2024
[j6]Hidetoshi Ikeda
, Yuta Mizukami, Masahiro Sakamoto, Takumi Saeki, Hokyoo Lee, Masakazu Hori:
Page Turning Using Assistive Robot with Low-Degree-of-Freedom Hand. Sensors 24(19): 6162 (2024)- [c8]Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri:
Development and Implementation Results of a DX Literacy Standard Skills Survey Using Generative AI. IIAI-AAI 2024: 166-171 - 2023
- [c7]Masahiro Sakamoto, Yukihiro Matsubara, Kousuke Mouri:
Learning Analysis infrastructure to support optimal learning based on IRT and Video Enrollment Data. ICCE 2023
2010 – 2019
- 2015
- [j5]Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa:
A Sigma-Delta Domain Lowpass Wave Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 167-176 (2015) - 2014
- [c6]Hiroshi Sugimura, Kazuki Utsumi, Masayuki Kaneko, Kazuki Arima, Masahiro Sakamoto, Yuki Imaizumi, Tomoki Watanabe, Masao Isshiki:
Development of immersive display system of web service in living space. GCCE 2014: 49-50 - 2012
- [j4]Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa:
Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1952-1965 (2012) - [j3]Hisato Fujisaka, Masahiro Sakamoto, Chang-Jun Ahn, Takeshi Kamio, Kazuhisa Haeiwa:
Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part II: Multiplication and Algebraic Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1966-1979 (2012)
2000 – 2009
- 2004
- [c5]Hisato Fujisaka, Daisuke Hamano, Masahiro Sakamoto, Takeshi Kamio:
A binary-quantized pseudo-diffusion system. ISCAS (4) 2004: 720-723 - [c4]Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka:
A design of 4-operand redundant binary parallel adder using neuron MOS. ISCAS (2) 2004: 793-796 - 2002
- [j2]Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue:
Bit-Stream Signal Processing Circuits and Their Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 853-860 (2002) - [j1]Masahiro Sakamoto, Daisuke Hamano, Mititada Morisue:
Design of a multiple-operand redundant binary adder. Syst. Comput. Jpn. 33(10): 1-9 (2002) - [c3]Yuji Hidaka, Hisato Fujisaka, Masahiro Sakamoto, Mititada Morisue:
Piecewise linear operations on sigma-delta modulated signals. ICECS 2002: 983-986
1990 – 1999
- 1999
- [c2]Hisato Fujisaka, Naoyuki Masuda, Masahiro Sakamoto, Mititada Morisue:
Arithmetic circuits for single-bit digital signal processing. ICECS 1999: 1389-1392 - 1998
- [c1]Mititada Morisue, Jun Endo, Toshimitu Morooka, Nobuhiro Shimizu, Masahiro Sakamoto:
A Josephson Ternary Memory Circuit. ISMVL 1998: 19-24
Coauthor Index
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