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Akinori Kanasugi
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2020 – today
- 2020
- [j15]Takahito Hayashi, Akinori Kanasugi:
A design of EPIC type processor based on MIPS architecture. Artif. Life Robotics 25(1): 59-63 (2020) - [j14]Hiroaki Kaneko, Akinori Kanasugi:
An integrated machine code monitor for a RISC-V processor on an FPGA. Artif. Life Robotics 25(3): 427-433 (2020)
2010 – 2019
- 2018
- [c7]Akihiko Tsukahara, Akinori Kanasugi:
Design of Approximate Arithmetic Circuits within Tolerance. CEEC 2018: 79-82 - 2015
- [j13]Takahiko Sega, Akinori Kanasugi, Ki Ando:
Generator of dynamically reconfigurable processor. Artif. Life Robotics 20(2): 103-108 (2015) - [j12]Akinori Kanasugi, Akihiko Tsukahara, Ki Ando:
Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. Nat. Comput. 14(4): 593-601 (2015) - [c6]Akihiko Tsukahara, Akinori Kanasugi:
Design of a Real Coded GA Processor. IJCCI (ECTA) 2015: 334-339 - 2014
- [j11]Akihiko Tsukahara, Akinori Kanasugi:
A novel architecture of dynamically reconfigurable fused multiply-adder for digital signal processing. Artif. Life Robotics 19(3): 233-238 (2014) - [j10]Ki Ando, Hidekazu Uchida, Shamim Ahmed, Koichi Nishigaki, Osamu Takei, Akinori Kanasugi:
Position detection method for microwell chip on microscope stage by photon multiplier tube. Artif. Life Robotics 19(3): 239-243 (2014) - [j9]Kengo Nishijima, Akinori Kanasugi, Ki Ando:
Accuracy improvement of genetic algorithm for obtaining floating-point solution. Artif. Life Robotics 19(4): 328-332 (2014) - 2012
- [j8]Akira Murayama, Akinori Kanasugi:
A Processor for GA based on Redundant Binary Number using FPGA. J. Next Gener. Inf. Technol. 3(3): 1-9 (2012) - 2010
- [j7]Yuki Hayakawa, Akinori Kanasugi:
A dynamically reconfigurable processor for H.264/AVC image prediction. Artif. Life Robotics 15(2): 147-150 (2010) - [j6]Akira Murayama, Akinori Kanasugi:
A novel coding method for genetic algorithms based on redundant binary numbers. Artif. Life Robotics 15(3): 306-308 (2010) - [j5]Toshiyuki Ishimura, Akinori Kanasugi:
A Design and Simulation for Dynamically Reconfigurable Systolic Array. Int. J. Inf. Process. Manag. 1(2): 18-24 (2010) - [j4]Masanao Aoshima, Akinori Kanasugi:
A Processor for Genetic Algorithm Based on Redundant Binary Number. J. Next Gener. Inf. Technol. 1(3): 66-74 (2010) - [c5]Yuki Hayakawa, Akinori Kanasugi:
Design of Dynamically Reconfigurable Processor for the H.264/AVC Image Prediction and De-blocking Filter. CSE 2010: 127-131
2000 – 2009
- 2007
- [j3]Akinori Kanasugi, Akihiko Tsukahara:
A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory. J. Convergence Inf. Technol. 2(1): 4-15 (2007) - [c4]Akihiko Tsukahara, Akinori Kanasugi:
Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy. FBIT 2007: 785-789 - [c3]Akinori Kanasugi, Mitsuhiro Matsumoto:
Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board. RSEISP 2007: 594-602 - 2001
- [c2]Akinori Kanasugi:
A Design of Architecture for Rough Set Processor. JSAI Workshops 2001: 406-412
1990 – 1999
- 1998
- [c1]Akinori Kanasugi, Takashi Shimayama, Naoshi Nakaya, Takeshi Iizuka:
A Genetic Algorithm for Switchbox Routing Problem. Rough Sets and Current Trends in Computing 1998: 247-254 - 1997
- [j2]Mititada Morisue, Masayuki Yamadaya, Hiroshi Noguchi, Akinori Kanasugi:
A digital application of chaotic oscillation modes in Josephson circuit. Int. J. Intell. Syst. 12(4): 267-290 (1997)
1980 – 1989
- 1988
- [j1]Koichi Yamashita, Akinori Kanasugi, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura, Takehide Shirato:
A wafer-scale 170000-gate FFT processor with built-in test circuits. IEEE J. Solid State Circuits 23(2): 336-342 (1988)
Coauthor Index
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