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ORCIDMitesh R. Meswani
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2010 – 2019
- 2017
[c16]Mahzabeen Islam, Krishna M. Kavi, Mitesh R. Meswani, Soumik Banerjee, Nuwan Jayasena:
HBM-Resident Prefetching for Heterogeneous Memory System. ARCS 2017: 124-136- [c15]Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul
, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan:
Design and Analysis of an APU for Exascale Computing. HPCA 2017: 85-96 - [c14]Jee Ho Ryoo, Mitesh R. Meswani, Andreas Prodromou, Lizy K. John:
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization. HPCA 2017: 349-360 - [c13]Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen:
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. HPCA 2017: 433-444 - 2016
- [c12]Jee Ho Ryoo, Mitesh R. Meswani, Reena Panda, Lizy K. John:
POSTER: SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization. PACT 2016: 435-437 - [c11]Mahzabeen Islam, Soumik Banerjee, Mitesh R. Meswani, Krishna M. Kavi:
Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization. MEMSYS 2016: 220-231 - [c10]Manish Gupta, David Roberts, Mitesh R. Meswani, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta:
Reliability and Performance Trade-off Study of Heterogeneous Memories. MEMSYS 2016: 395-401 - 2015
- [c9]Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh:
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. HPCA 2015: 126-136 - [c8]Ahsen J. Uppal, Mitesh R. Meswani:
Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories. MEMSYS 2015: 206-219 - 2014
- [c7]Mayank Daga, Mark Nutter, Mitesh R. Meswani:
Efficient breadth-first search on a heterogeneous processor. IEEE BigData 2014: 373-382 - [c6]Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski:
Toward efficient programmer-managed two-level memory hierarchies in exascale computers. Co-HPC@SC 2014: 9-16 - 2013
- [j1]Mitesh R. Meswani, Laura Carrington, Didem Unat, Allan Snavely, Scott B. Baden, Stephen Poole:
Modeling and predicting performance of high performance computing applications on hardware accelerators. Int. J. High Perform. Comput. Appl. 27(2): 89-108 (2013) - [c5]Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Mitesh R. Meswani, Mark Nutter, Mike Ignatowski:
A new perspective on processing-in-memory architecture design. MSPC@PLDI 2013: 7:1-7:3 - 2012
- [c4]Mitesh R. Meswani, Laura Carrington, Didem Unat, Allan Snavely, Scott B. Baden, Stephen Poole:
Modeling and Predicting Performance of High Performance Computing Applications on Hardware Accelerators. IPDPS Workshops 2012: 1828-1837 - 2011
- [c3]Michael Laurenzano, Mitesh R. Meswani, Laura Carrington, Allan Snavely, Mustafa M. Tikir, Stephen Poole:
Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling. Euro-Par (1) 2011: 79-90 - [c2]Mitesh R. Meswani, Laura Carrington, Didem Unat, Allan Snavely, Scott B. Baden, Stephen Poole:
Modeling and predicting application performance on hardware accelerators. IISWC 2011: 73 - 2010
- [c1]Catherine Olschanowsky, Allan Snavely, Mitesh R. Meswani, Laura Carrington:
PIR: PMaC's Idiom Recognizer. ICPP Workshops 2010: 189-196
Coauthor Index
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