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2010 – 2019
- 2013
[j4]Raphael Poss
, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. Microprocess. Microsystems 37(8-C): 1090-1101 (2013)- [c6]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - A simulation environment for multi-core research and education. ICSAMOS 2013: 80-87 - [i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) - 2012
- [c5]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 - [c4]Raphael Poss, Mike Lankamp, Muhammad Irfan Uddin, Jaroslav Sykora, Leos Kafka:
Heterogeneous integration to simplify many-core architecture simulations. RAPIDO 2012: 17-24
2000 – 2009
- 2009
- [j3]Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp:
Implementation and evaluation of a microthread architecture. J. Syst. Archit. 55(3): 149-161 (2009) - [j2]Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra:
An implementation of the SANE Virtual Processor using POSIX threads. J. Syst. Archit. 55(3): 162-169 (2009) - [j1]Chris R. Jesshope, Mike Lankamp, Li Zhang:
The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Comput. Archit. News 37(2): 38-45 (2009) - [c3]Chris R. Jesshope, Mike Lankamp, Li Zhang:
Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257 - [c2]Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang:
Making multi-cores mainstream - from security to scalability. PARCO 2009: 16-31 - 2008
- [c1]Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang:
A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9
Coauthor Index
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