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Journal Articles
- 2016
[j2]Yoongu Kim, Weikun Yang, Onur Mutlu:
Ramulator: A Fast and Extensible DRAM Simulator. IEEE Comput. Archit. Lett. 15(1): 45-49 (2016)- 2011
- [j1]Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
:
Thread Cluster Memory Scheduling. IEEE Micro 31(1): 78-89 (2011)
Conference and Workshop Papers
- 2022
- [c14]Andreas Kogler, Jonas Juffinger, Salman Qazi, Yoongu Kim, Moritz Lipp, Nicolas Boichat, Eric Shiu, Mattias Nissler, Daniel Gruss:
Half-Double: Hammering From the Next Row Over. USENIX Security Symposium 2022: 3807-3824 - 2015
- [c13]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu:
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. HPCA 2015: 489-501 - 2014
- [c12]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM performance by parallelizing refreshes with accesses. HPCA 2014: 356-367 - [c11]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ISCA 2014: 361-372 - [c10]Samira Manabi Khan, Donghyuk Lee, Yoongu Kim, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu:
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study. SIGMETRICS 2014: 519-532 - 2013
- [c9]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-latency DRAM: A low latency and low cost DRAM architecture. HPCA 2013: 615-626 - [c8]Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu:
MISE: Providing performance predictability and improving fairness in shared main memory systems. HPCA 2013: 639-650 - [c7]Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu:
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms. ISCA 2013: 60-71 - [c6]Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Linearly compressed pages: a low-complexity, low-latency main memory compression framework. MICRO 2013: 172-184 - [c5]Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization. MICRO 2013: 185-197 - 2012
- [c4]Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu:
A case for exploiting subarray-level parallelism (SALP) in DRAM. ISCA 2012: 368-379 - 2010
- [c3]Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter:
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. HPCA 2010: 1-12 - [c2]Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter:
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. MICRO 2010: 65-76 - 2004
- [c1]Chanjung Park, Seog Park, Yoongu Kim:
S-COI : The Secure Conflicts of Interest Model for Multilevel Secure Database Systems. DASFAA 2004: 146-153
Parts in Books or Collections
- 2014
- [p1]Yoongu Kim, Onur Mutlu:
Memory Systems. Computing Handbook, 3rd ed. (1) 2014: 18: 1-21
Informal and Other Publications
- 2018
- [i11]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. CoRR abs/1805.01289 (2018) - [i10]Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu:
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism. CoRR abs/1805.01966 (2018) - [i9]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin K. Chang, Onur Mutlu:
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins. CoRR abs/1805.03047 (2018) - [i8]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost. CoRR abs/1805.03048 (2018) - [i7]Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
RowClone: Accelerating Data Movement and Initialization Using DRAM. CoRR abs/1805.03502 (2018) - [i6]Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu:
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems. CoRR abs/1805.05926 (2018) - 2017
- [i5]Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM Performance by Parallelizing Refreshes with Accesses. CoRR abs/1712.07754 (2017) - 2016
- [i4]Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. CoRR abs/1601.06352 (2016) - [i3]Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu:
Tiered-Latency DRAM (TL-DRAM). CoRR abs/1601.06903 (2016) - [i2]Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu:
RowHammer: Reliability Analysis and Security Implications. CoRR abs/1603.00747 (2016) - [i1]Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Manabi Khan, Vivek Seshadri, Kevin Kai-Wei Chang, Onur Mutlu:
Adaptive-Latency DRAM (AL-DRAM). CoRR abs/1603.08454 (2016)
Coauthor Index
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