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2020 – today
- 2024
[j10]Jilin Zhang
, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, Hong Chen:
ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications. IEEE J. Solid State Circuits 59(8): 2717-2729 (2024)- [c15]Ziyi Liu, Yiwei Du, Renrong Liang, Zhigang Zhang, Liyang Pan, Jianshi Tang, Renrong Liang, Bin Gao, Qi Hu, Jun Xu, He Qian, Huaqiang Wu, Yuegang Zhang:
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j9]Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu:
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5339-5351 (2023) - [c14]Tao Huang, Run Run, Yi Hu, Li Yin, Liyang Pan, Guolin Li, Xiang Xie:
An Energy-Efficient Gain-Cell Embedded DRAM Design with Weight Encoding for CNN Applications. ICTA 2023: 1-2 - [c13]Jilin Zhang, Dexuan Huo, Jian Zhang, Chunqi Qian, Qi Liu, Liyang Pan, Zhihua Wang, Ning Qiao, Kea-Tiong Tang, Hong Chen:
ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications. ISSCC 2023: 336-337
2010 – 2019
- 2019
- [c12]Youyou Lu, Jiacheng Zhang, Zhe Yang, Liyang Pan, Jiwu Shu:
OCStore: Accelerating Distributed Object Storage with Open-Channel SSDs. ICDCS 2019: 271-281 - 2016
- [j8]Haozhi Ma, Lifang Liu, Liyang Pan, Jun Xu:
LSB page refresh based retention error recovery scheme for MLC NAND Flash. Sci. China Inf. Sci. 59(4): 042408:1-042408:11 (2016) - [c11]Xingjun Xue, Shujie Yang, Dong Wu, Liyang Pan, Zheyao Wang:
Fabrication of ultra-thin silicon chips using thermally decomposable temporary bonding adhesive. IEEE SENSORS 2016: 1-3 - 2015
- [j7]Lifang Liu, Dong Wu, Xuemei Liu, Zongliang Huo, Ming Liu, Liyang Pan:
A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time. Sci. China Inf. Sci. 58(4): 1-8 (2015) - [c10]Cui Huang, Dong Wu, Liyang Pan, Zheyao Wang:
Air-gap/SiO2 liner TSVs with improved electrical performance. 3DIC 2015: TS8.7.1-TS8.7.5 - [c9]Haozhi Ma, Zhongyi Gao, Liyang Pan, Jun Xu:
Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories. ASICON 2015: 1-4 - [c8]Qian Lei, Liji Wu, Shaohui Zhang, Xiangmin Zhang, Xiangyu Li, Liyang Pan, Zhimeng Dong:
Software Hardware Co-design for Side-Channel Analysis Platform on Security Chips. CIS 2015: 398-401 - [c7]Wenqiang Luo, Fang-Yuan Yuan, Huaqiang Wu, Liyang Pan, Ning Deng, Fei Zeng, Rongshan Wei, Xuanjing Cai:
Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT: PSS/Ta memristor. NVMTS 2015: 1-4 - 2014
- [j6]Fengying Qiao, Liyang Pan, Xiao Yu, Haozhi Ma, Dong Wu, Jun Xu:
Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology. Sci. China Inf. Sci. 57(6): 1-9 (2014) - [j5]Lifang Liu, Antonio Arreghini, Geert Van den Bosch, Liyang Pan, Jan Van Houdt:
Assessment methodology of the lateral migration component in data retention of 3D SONOS memories. Microelectron. Reliab. 54(9-10): 1697-1701 (2014) - [j4]Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He:
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2629-2634 (2014) - [c6]Cencen Gao, Dong Wu, Hui Liu, Nan Xie, Liyang Pan:
An ultra-low-power extended counting ADC For large scale sensor arrays. ISCAS 2014: 81-84 - 2011
- [j3]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. J. Electron. Test. 27(5): 647-655 (2011) - [j2]Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. J. Electron. Test. 27(5): 679 (2011) - [c5]Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan:
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). FPGA 2011: 281 - 2010
- [c4]Peijun Liu, Xueqiang Wang, Dong Wu, Zhigang Zhang, Liyang Pan:
A novel high-speed and low-power negative voltage level shifter for low voltage applications. ISCAS 2010: 601-604
2000 – 2009
- 2009
- [j1]Xueqiang Wang, Liyang Pan, Dong Wu, Chaohong Hu, Runde Zhou:
A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 865-869 (2009) - [c3]Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Runde Zhou:
Embedded high-speed BCH decoder for new-generation NOR flash memories. CICC 2009: 195-198 - 2008
- [c2]Liyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu, Jun Xu:
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application. CICC 2008: 197-200 - 2006
- [c1]Liyang Pan, Dong Wu, Guangjun Yang, Lei Sun, Huiqing Pang, Jun Zhu:
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory. CICC 2006: 305-308
Coauthor Index
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