"A chip-level path-delay-distribution based Dual-VDD method for low power ..."

Jianfeng Zhu et al. (2011)

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DOI: 10.1145/1950413.1950475

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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  - conf/fpga/ZhuWYYHP11
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Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan:
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). FPGA 2011: 281

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