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ORCIDDominik Kasprowicz
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2010 – 2019
- 2019
[j3]Dominik Kasprowicz
:
Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1493-1500 (2019)- [c8]Dominik Kasprowicz:
Semiconductor Device Parameter Extraction Based on I-V Measurements and Simulation. MIXDES 2019: 321-326 - 2017
- [c7]Dominik Kasprowicz:
Variability-aware table-based DC model of a dual-gate transistor. MIXDES 2017: 154-158 - 2015
- [c6]Dominik Kasprowicz:
Channel charge model of a dual-gate junctionless transistor. MIXDES 2015: 216-221 - 2014
- [j2]Dominik Kasprowicz, Hilekaan Wada:
Methods for automated detection of plagiarism in integrated-circuit layouts. Microelectron. J. 45(9): 1212-1219 (2014) - 2013
- [c5]Dominik Kasprowicz, Bartosz Swacha:
VeSFET as an analog-circuit component. DDECS 2013: 199-204 - [c4]Dominik Kasprowicz, Hilekaan Wada:
Computer-aided detection of plagiarism in integrated-circuit layouts. MIXDES 2013: 213-217
2000 – 2009
- 2009
- [c3]Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel:
Adder Circuits with Transistors using Independently Controlled Gates. ISCAS 2009: 449-452 - 2008
- [c2]Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz:
Is there always performance overhead for regular fabric? ICCD 2008: 557-562 - 2003
- [j1]Dominik Kasprowicz, Witold A. Pleskacz:
Improvement of integrated circuit testing reliability by using the defect based approach. Microelectron. Reliab. 43(6): 945-953 (2003) - 2001
- [c1]Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for Defect Based Testing. DFT 2001: 384-
Coauthor Index
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