default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJae-Won Nam
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j13]Jae-Yun Park, Jae-Won Nam:
A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4663-4667 (2024)- 2023
- [j12]Jin-Won Hyun
, Jae-Won Nam:
AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure. IEEE Access 11: 58850-58862 (2023) - [j11]Jae-Yun Park, Su-Hyeon Kim, Hyunyoung Yoo, Jae-Won Nam:
Analysis of Quarter Method Applied ROM-Based DDFS Architecture. IEEE Access 11: 117137-117148 (2023) - [j10]Dana Kim, Jong-Phil Hong, Jiwon Lee, Jae-Won Nam:
High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3917-3921 (2023) - [c10]Jin-Won Hyun, Jae-Won Nam:
Regression Model-based VCO Design Optimization Technique. ICEIC 2023: 1-3 - [i1]Seungmo Kim, Yeonho Jeong, Jae-Won Nam:
Optimizing EV Chargers Location via Integer Programming. CoRR abs/2303.09947 (2023) - 2022
- [j9]Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong:
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique. IEEE Access 10: 22311-22319 (2022) - [j8]Young-Kyun Cho, Jae-Won Nam, Sang-Won Lee:
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 819-823 (2022) - 2021
- [c9]Soowang Park, Jae-Won Nam, Sandeep K. Gupta:
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. ASP-DAC 2021: 29-34 - [c8]Hee won Kwon, Jae-Won Nam, Joongheon Kim, Youn Kyu Lee:
Generative Adversarial Attacks on Fingerprint Recognition Systems. ICOIN 2021: 483-485 - [c7]Jae-Won Nam, Youn Kyu Lee:
Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization. ICOIN 2021: 874-876 - 2020
- [j7]Jae-Won Nam, Mike Shuo-Wei Chen:
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. IEEE J. Solid State Circuits 55(3): 557-566 (2020)
2010 – 2019
- 2019
- [c6]Jae-Won Nam, Mike Shuo-Wei Chen:
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. CICC 2019: 1-4 - 2018
- [j6]Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53(6): 1765-1779 (2018) - 2016
- [j5]Jae-Won Nam, Mike Shuo-Wei Chen:
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1628-1638 (2016) - [c5]Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits 2016: 1-2 - 2013
- [c4]Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen:
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. CICC 2013: 1-4 - 2012
- [j4]Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon:
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 741-745 (2012) - 2011
- [j3]Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon:
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. Microelectron. J. 42(11): 1225-1230 (2011) - [j2]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. Microelectron. J. 42(12): 1335-1342 (2011) - [c3]Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon:
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. ISOCC 2011: 405-407 - 2010
- [j1]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 502-506 (2010) - [c2]Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon:
A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. CICC 2010: 1-4
2000 – 2009
- 2009
- [c1]Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon:
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. ESSCIRC 2009: 468-471
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-15 20:39 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
