"A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital ..."

Young-Kyun Cho et al. (2010)

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DOI: 10.1109/TCSII.2010.2048387

access: closed

type: Journal Article

metadata version: 2023-09-30

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Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 502-506 (2010)

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