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ORCIDShuo Wang 0009
Person information
- affiliation: Peking University, School of EECS, Beijing, China
- affiliation (former): University of Southern California, Los Angeles, CA, USA
Other persons with the same name
- Shuo Wang — disambiguation page
- Shuo Wang 0001
![[0000-0002-1390-9219]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-1390-9219")
— Chinese Academy of Sciences, Institute of Automation, State Key Laboratory of Management and Control for Complex Systems, Beijing, China - Shuo Wang 0002 — Hong Kong Polytechnic University, Department of Land Surveying and Geo-Informatics, Hong Kong (and 3 more)
- Shuo Wang 0003 — University of Florida, Department of Electrical and Computer Engineering, Gainesville, FL, USA (and 3 more)
- Shuo Wang 0004 — Beijing University of Posts and Telecommunications, Department of Information and Communications Engineering, China
- Shuo Wang 0005 — University of Birmingham, School of Computer Science, UK
- Shuo Wang 0006 — Beijing University of Posts and Telecommunications, State Key Laboratory of Networking and Switching Technology, China
- Shuo Wang 0007 — University of Bonn, Germany
- Shuo Wang 0008 — University of Science and Technology of China, School of Information Science and Technology, Hefei, China (and 1 more)
- Shuo Wang 0010 — Beijing, Normal University, Beijing, China
- Shuo Wang 0011 — Fudan University, Digital Medical Research Center, School of Basic Medical Sciences, Shanghai Key Laboratory of MICCAI, China (and 1 more)
- Shuo Wang 0012 — Monash University, Melbourne, CSIRO, Data61, Cybersecurity CRC, Australia (and 1 more)
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2020 – today
- 2021
[c14]Ye Zhang, Shuo Wang, Xian Zhang, Jiangbin Dong, Xingzhong Mao, Fan Long, Cong Wang, Dong Zhou, Mingyu Gao, Guangyu Sun:
PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture. ISCA 2021: 416-428- 2020
- [c13]Size Zheng, Yun Liang, Shuo Wang, Renze Chen, Kaiwen Sheng:
FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System. ASPLOS 2020: 859-873
2010 – 2019
- 2019
- [c12]Runbin Shi, Junjie Liu, Hayden Kwok-Hay So, Shuo Wang, Yun Liang:
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. DAC 2019: 182 - [c11]Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang:
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. FPGA 2019: 33-42 - [c10]Shuo Wang, Yun Liang, Wei Zhang:
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications. HPCA 2019: 199-210 - [i3]Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang:
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. CoRR abs/1909.13396 (2019) - 2018
- [j2]Yun Liang, Shuo Wang, Wei Zhang:
FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs. IEEE Trans. Computers 67(12): 1750-1764 (2018) - [c9]Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha:
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. ACA 2018: 95-108 - [c8]Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang:
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. FPGA 2018: 11-20 - [c7]Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang:
Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. ICLR (Workshop) 2018 - [i2]Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Yanzhi Wang, Qinru Qiu, Yun Liang:
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. CoRR abs/1803.06305 (2018) - [i1]Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang:
Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. CoRR abs/1803.07661 (2018) - 2017
- [c6]Shuo Wang, Yun Liang, Wei Zhang:
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. DAC 2017: 27:1-27:6 - [c5]Shuo Wang, Yun Liang:
A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model. DAC 2017: 28:1-28:6 - [c4]Shuo Wang, Yun Liang:
A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). FPGA 2017: 285-286 - 2016
- [j1]Yun Liang, Shuo Wang:
Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs. J. Comput. Sci. Technol. 31(1): 36-49 (2016) - [c3]Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li:
Performance-centric register file design for GPUs using racetrack memory. ASP-DAC 2016: 25-30 - 2015
- [c2]Shuo Wang, Yanzhi Wang, Xue Lin, Massoud Pedram:
Hierarchical Deployment and Control of Energy Storage Devices in Data Centers. CLOUD 2015: 805-812 - [c1]Yun Liang, Shuo Wang:
Quantitative performance and power analysis of LTE using high level synthesis. ASICON 2015: 1-4
Coauthor Index
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