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2010 – 2019
- 2011
[j2]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa
, Shin'ichi Miura, Taisuke Boku:
Peach: A Multicore Communication System on Chip with PCI Express. IEEE Micro 31(6): 39-50 (2011)- [c4]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. COOL Chips 2011: 1-3 - [c3]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268 - 2010
- [j1]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010)
2000 – 2009
- 2009
- [c2]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2005
- [c1]Makoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe:
Elastic shared resource scheduling SOC interconnect architecture for real-time system. CICC 2005: 787-790
Coauthor Index
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