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ORCIDRajeevan Chandel
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2020 – today
- 2022
[j14]Ajay Kumar
, Rajeevan Chandel, Rohit Dhiman:
Proposal and analysis of carbon nanotube based differential multibit through glass vias. Microelectron. J. 126: 105500 (2022)- [c8]Deepanshu Kaushal, Rajeevan Chandel:
Improving the Flare Perturbation Response of Gasket Monopole Antenna for Custom Frequency Solutions. iSES 2022: 158-163 - 2021
- [j13]Neha Sharma, Rajeevan Chandel:
Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS. Int. J. Model. Simul. Sci. Comput. 12(4): 2150029:1-2150029:17 (2021) - [j12]Ashish Singh, Rajeevan Chandel, Rohit Dhiman:
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects. Integr. 80: 29-40 (2021) - [j11]Sunil Jadav, Shubham Tayal, Rajeevan Chandel, Munish Vashishath:
High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects. Microelectron. J. 107: 104941 (2021) - [j10]Girish Kumar Mekala, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel:
A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects. Microelectron. J. 118: 105294 (2021)
2010 – 2019
- 2018
- [j9]Yash Agrawal, Girish Kumar Mekala, Rajeevan Chandel:
A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects. Circuits Syst. Signal Process. 37(4): 1359-1382 (2018) - 2017
- [j8]Girish Kumar Mekala, Yash Agrawal, Rajeevan Chandel:
Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects. IET Circuits Devices Syst. 11(3): 232-240 (2017) - [c7]Parmjit Singh, Rajeevan Chandel, Neha Sharma:
Stability analysis of SRAM cell using CNT and GNR field effect transistors. IC3 2017: 1-6 - 2016
- [c6]Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel:
Performance Analysis of Top-Contact MLGNR Based Interconnects. iNIS 2016: 11-16 - [c5]Sanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel:
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications. ISVLSI 2016: 355-360 - 2015
- [j7]Rohit Dhiman, Rajeevan Chandel:
Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications. Circuits Syst. Signal Process. 34(1): 21-40 (2015) - [c4]Yash Agrawal, Rajeevan Chandel, Girish Kumar Mekala:
Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System. iNIS 2015: 297-302 - [c3]Girish Kumar Mekala, Rajeevan Chandel, Yash Agrawal:
Timing and Stability Analysis of Carbon Nanotube Interconnects. iNIS 2015: 308-313 - 2014
- [i1]Sunil Jadav, Munish Vashistah, Rajeevan Chandel:
Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique. CoRR abs/1412.7818 (2014) - 2012
- [j6]Sandeep Singh Gill, Rajeevan Chandel, Ashwani Kumar Chandel:
Netlist bipartitioning using particle swarm optimisation technique. Int. J. Artif. Intell. Soft Comput. 3(1): 1-15 (2012) - [j5]Rohit Dhiman, Rajeevan Chandel:
Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications. J. Low Power Electron. 8(1): 39-46 (2012) - 2011
- [c2]Tafseer Alam, Rohit Dhiman, Rajeevan Chandel:
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect. ICWET 2011: 1157-1160 - 2010
- [j4]Kiran K. Chaddha, Rajeevan Chandel:
Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique. J. Low Power Electron. 6(4): 482-490 (2010) - [j3]Ashutosh Nandi, Rajeevan Chandel:
Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications. J. Low Power Electron. 6(4): 513-520 (2010) - [c1]Gargi Khanna, Rajeevan Chandel, Ashwani Kumar Chandel:
Impact of skew and jitter on the performance of VLSI interconnects. APCCAS 2010: 1223-1226
2000 – 2009
- 2007
- [j2]Rajeevan Chandel, Sankar Sarkar, Ashwani Kumar Chandel:
Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects. J. Low Power Electron. 3(3): 337-344 (2007) - [j1]Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal:
An analysis of interconnect delay minimization by low-voltage repeater insertion. Microelectron. J. 38(4-5): 649-655 (2007)
Coauthor Index
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