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Journal Articles
- 2012
[j7]Moo-young Kim, Hokyu Lee, Chulwoo Kim:
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 737-741 (2012)- 2011
- [j6]Moo-young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim:
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1438-1447 (2011) - 2009
- [j5]Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1461-1469 (2009) - 2008
- [j4]Inhwa Jung, Gunok Jung, Janghoon Song, Moo-young Kim, Junyoung Park, Sung-Bae Park, Chulwoo Kim:
A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 116-120 (2008) - 2007
- [j3]Inhwa Jung, Moo-young Kim, Chulwoo Kim:
Sptpl: a New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SOC). J. Circuits Syst. Comput. 16(2): 169-179 (2007) - 2006
- [j2]Inhwa Jung, Moo-young Kim, Dongsuk Shin, Seon Wook Kim, Chulwoo Kim:
A New Energy x Delay-Aware Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(6): 1552-1557 (2006) - [j1]Jin-Han Kim, Young-Ho Kwak, Moo-young Kim, Soo-Won Kim, Chulwoo Kim:
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEE J. Solid State Circuits 41(9): 2077-2082 (2006)
Conference and Workshop Papers
- 2008
- [c3]Inhwa Jung, Moo-young Kim, Chulwoo Kim:
A 1.2GHz delayed clock generator for high-speed microprocessors. ASP-DAC 2008: 95-96 - 2007
- [c2]Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. CICC 2007: 369-372 - 2005
- [c1]Moo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim:
Differential Pass Transistor Pulsed Latch. SoCC 2005: 295-300
Coauthor Index
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