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ORCIDZvika Guz
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2010 – 2019
- 2018
[j5]Zvika Guz, Harry (Huan) Li, Anahita Shayesteh, Vijay Balakrishnan:
Performance Characterization of NVMe-over-Fabrics Storage Disaggregation. ACM Trans. Storage 14(4): 31:1-31:18 (2018)- 2017
- [c11]Keren Ouaknine, Oran Agra, Zvika Guz:
Optimization of RocksDB for Redis on Flash. ICCDA 2017: 155-161 - [c10]Zvika Guz, Harry (Huan) Li, Anahita Shayesteh, Vijay Balakrishnan:
NVMe-over-fabrics performance characterization and the path to low-overhead flash disaggregation. SYSTOR 2017: 16:1-16:9 - 2015
- [c9]Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan:
Performance Characterization of Hyperscale Applicationson on NVMe SSDs. SIGMETRICS 2015: 473-474 - [c8]Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan:
Performance analysis of NVMe SSDs and their implication on real world databases. SYSTOR 2015: 6:1-6:11 - [c7]Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan:
System-Level Characterization of Datacenter Applications. ICPE 2015: 27-38 - 2014
- [c6]Adwait Jog, Evgeny Bolotin, Zvika Guz, Mike Parker, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das:
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications. GPGPU@ASPLOS 2014: 1 - 2010
- [c5]Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Threads vs. caches: Modeling the behavior of parallel workloads. ICCD 2010: 274-281
2000 – 2009
- 2009
- [j4]Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. 8(1): 25-28 (2009) - [c4]Haggai Eran
, Ohad Lutzky, Zvika Guz, Idit Keidar:
Transactifying Apache's cache module. SYSTOR 2009: 2 - 2008
- [j3]Zvika Guz:
Review of SPAA'08. SIGACT News 39(4): 66-68 (2008) - [c3]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10 - 2007
- [j2]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. 6(1): 21-24 (2007) - [j1]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: 90941:1-90941:15 (2007) - [c2]Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126 - 2006
- [c1]Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny:
Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14
Coauthor Index
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