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ORCIDTameesh Suri
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2010 – 2019
- 2017
[c8]Tameesh Suri, Aneesh Aggarwal:
Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. ARCS 2017: 99-110- 2015
- [c7]Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan:
Performance Characterization of Hyperscale Applicationson on NVMe SSDs. SIGMETRICS 2015: 473-474 - [c6]Qiumin Xu, Huzefa Siyamwala, Mrinmoy Ghosh, Tameesh Suri, Manu Awasthi, Zvika Guz, Anahita Shayesteh, Vijay Balakrishnan:
Performance analysis of NVMe SSDs and their implication on real world databases. SYSTOR 2015: 6:1-6:11 - [c5]Manu Awasthi, Tameesh Suri, Zvika Guz, Anahita Shayesteh, Mrinmoy Ghosh, Vijay Balakrishnan:
System-Level Characterization of Datacenter Applications. ICPE 2015: 27-38 - 2014
- [j3]Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh
, Tameesh Suri:
SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors. IEEE Trans. Computers 63(2): 484-496 (2014) - 2011
- [c4]Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Tameesh Suri:
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. Conf. Computing Frontiers 2011: 37 - 2010
- [j2]Tameesh Suri, Aneesh Aggarwal:
Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration. Int. J. Parallel Program. 38(3-4): 203-224 (2010)
2000 – 2009
- 2009
- [c3]Tameesh Suri, Aneesh Aggarwal:
Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. Conf. Computing Frontiers 2009: 151-160 - [c2]Tameesh Suri, Aneesh Aggarwal:
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. VLSI Design 2009: 145-150 - 2008
- [c1]Tameesh Suri, Aneesh Aggarwal:
Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware. HiPC 2008: 365-377 - 2007
- [j1]Tameesh Suri:
Improving instruction level parallelism through reconfigurable units in superscalar processors. SIGARCH Comput. Archit. News 35(3): 20-27 (2007)
Coauthor Index
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