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Journal Articles
- 2013
[j4]Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko:
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. IEICE Trans. Electron. 96-C(1): 108-114 (2013)- 2000
- [j3]Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35(4): 564-571 (2000) - [j2]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma:
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. IEEE J. Solid State Circuits 35(8): 1159-1168 (2000) - 1998
- [j1]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma:
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. IEEE J. Solid State Circuits 33(11): 1650-1658 (1998)
Conference and Workshop Papers
- 2005
- [c1]Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta:
External memory BIST for system-in-package. ITC 2005: 10
Coauthor Index
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