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ORCIDD. Meganathan
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2020 – today
- 2020
[j8]D. R. Denslin Brabin
, J. Raja Paul Perinbam, D. Meganathan:
Watermark Visibility Adjustable RVW Scheme for JPEG Images. Wirel. Pers. Commun. 115(1): 187-202 (2020)
2010 – 2019
- 2019
- [j7]S. Jagannathan, Sathiesh Kumar Vajravelu, D. Meganathan:
Design and implementation of in-situ human-elephant conflict management system. J. Intell. Fuzzy Syst. 36(3): 2005-2013 (2019) - 2018
- [j6]Roy Francis, D. Meganathan:
An Improved ANFIS with Aid of ALO Technique for THD Minimization of Multilevel Inverters. J. Circuits Syst. Comput. 27(12): 1850193:1-1850193:25 (2018) - 2017
- [j5]D. R. Denslin Brabin, J. Raja Paul Perinbam, D. Meganathan:
A Block Based Reversible Data Hiding Scheme for Digital Images Using Optimal Value Computation. Wirel. Pers. Commun. 94(4): 2583-2596 (2017) - 2011
- [j4]D. Meganathan:
A 24.5 mW, 10-bit, 50 MS/sec CMOS pipelined analogue-to-digital converter. Int. J. High Perform. Syst. Archit. 3(4): 184-201 (2011)
2000 – 2009
- 2009
- [j3]D. Meganathan, J. Raja Paul Perinbam, R. Deepalakshmi:
High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC. Int. J. High Perform. Syst. Archit. 2(1): 1-15 (2009) - [j2]D. Meganathan, Amrith Sukumaran, M. M. Dinesh Babu, S. Moorthi, R. Deepalakshmi:
A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC. Microelectron. J. 40(10): 1417-1435 (2009) - 2008
- [j1]D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu, J. Raja Paul Perinbam:
A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter. J. Low Power Electron. 4(2): 208-227 (2008)
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