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ORCIDPaul T. Hulina
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1990 – 1999
- 1999
[c17]David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor:
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. ICCD 1999: 146-151- [c16]Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno:
Computing in Memory Architectures for Digital Image Processing. MTDT 1999: 8-15 - [c15]David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor:
Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. IEEE International Workshop on Rapid System Prototyping 1999: 52- - [c14]Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian:
A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. IEEE International Workshop on Rapid System Prototyping 1999: 222- - 1997
- [c13]Paul T. Hulina, David L. Landis:
An electronics manufacturing minor in engineering with emphasis on rapid prototyping. MSE 1997: 21-22 - [c12]David L. Landis, Paul T. Hulina:
A WWW facilitated rapid system prototyping class. MSE 1997: 99-100 - 1995
- [c11]Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor:
A comparative evaluation of software techniques to hide memory latency. HICSS (1) 1995: 229-241 - [c10]Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor:
Program Balance and Its Impact on High Performance RISC Architectures. HPCA 1995: 370-379 - 1994
- [j9]Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor:
Memory Latency Effects in Decoupled Architectures. IEEE Trans. Computers 43(10): 1129-1139 (1994) - [c9]Lizyamma Kurian, Bermjae Choi, Paul T. Hulina, Lee D. Coraor:
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. ICPP (1) 1994: 212-219 - [c8]Ali Berrached, Paul T. Hulina, Lee D. Coraor:
Structured Data Access Mechanisms for a Decoupled Computer Architecture. ICPP (2) 1994: 285-289 - 1992
- [j8]Paul T. Hulina, Lizyamma Kurian, Eugene B. John
, Lee D. Coraor:
Design and VLSI implementation of an access processor for a decoupled architecture. Microprocess. Microsystems 16(5): 237-247 (1992) - [c7]Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor:
Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. ISCA 1992: 236-245 - 1991
- [c6]Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun:
Performance Analysis of an Address Generation Coprocessor. ICPP (1) 1991: 136-143 - [c5]Lizyamma Kurian, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai:
Classification and Performance Evaluation of Instruction Buffering Techniques. ISCA 1991: 150-159 - 1990
- [j7]Paul T. Hulina, Lee D. Coraor:
Coprocessor architectures for efficient address computation and memory accessing. Comput. Syst. Sci. Eng. 5(3): 137-146 (1990)
1980 – 1989
- 1987
- [j6]Lee D. Coraor, Paul T. Hulina, Orlando A. Morean:
A General Model for Memory-Based Finite-State Machines. IEEE Trans. Computers 36(2): 175-184 (1987) - [c4]Paul T. Hulina, Lee D. Coraor:
A Hardware Memory Mapping Unit for Efficient Address Computation. ICPP 1987: 340-343 - 1985
- [c3]Lee D. Coraor, Paul T. Hulina:
A Reconfigurable Multiprocessor. ICPP 1985: 649-651
1970 – 1979
- 1973
- [j5]Jon G. Bredeson, Paul T. Hulina:
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops. IEEE Trans. Computers 22(5): 524-531 (1973) - 1972
- [j4]Jon G. Bredeson, Paul T. Hulina:
Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits. Inf. Control. 20(2): 114-124 (1972) - 1971
- [j3]Jon G. Bredeson, Paul T. Hulina:
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races. IEEE Trans. Computers 20(2): 225-226 (1971) - [j2]Jon G. Bredeson, Paul T. Hulina:
Generation of Prime Implicants by Direct Multiplication. IEEE Trans. Computers 20(4): 475-476 (1971) - 1970
- [j1]Paul T. Hulina, Jon G. Bredeson:
On Tracey's Internal State Assignment Method. IEEE Trans. Computers 19(5): 458 (1970) - [c2]James L. Elshoff, Paul T. Hulina:
The binary floating point digital differential analyzer. AFIPS Fall Joint Computing Conference 1970: 369-376 - [c1]Jon G. Bredeson, Paul T. Hulina:
Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits. SWAT 1970: 104-108
Coauthor Index
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