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ORCIDJon G. Bredeson
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1990 – 1999
- 1994
[c4]Hamid Barghi, William T. Cronenwett, Jon G. Bredeson:
Real-Time Study of a High Performance Protocol for Local/Metropolitan Ring Networks. LCN 1994: 139-145
1980 – 1989
- 1980
- [j12]John C. Sutton, Jon G. Bredeson:
Minimal Redundant Logic for High Reliability and Irredundant Testability. IEEE Trans. Computers 29(7): 648-656 (1980)
1970 – 1979
- 1978
- [j11]Zosimo Arevalo, Jon G. Bredeson:
A Method to Simplify a Boolean Function into a Near Minimal Sum-of-Products for Programmable Logic Arrays. IEEE Trans. Computers 27(11): 1028-1039 (1978) - [c3]N. W. Styer, Jon G. Bredeson:
Computer-assisted data communications engineering instruction. COMPSAC 1978: 620-625 - 1975
- [j10]Jon G. Bredeson:
Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops". IEEE Trans. Computers 24(11): 1142-1143 (1975) - 1974
- [j9]C. D. Latino, Jon G. Bredeson:
Comments on "Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks". IEEE Trans. Computers 23(12): 1326 (1974) - 1973
- [j8]Jon G. Bredeson, Paul T. Hulina:
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops. IEEE Trans. Computers 22(5): 524-531 (1973) - [c2]Jon G. Bredeson:
On Multiple Input Change Hazard-Free Combinatorial Switching Circuits without Feedback. SWAT 1973: 56-63 - 1972
- [j7]Jon G. Bredeson, Paul T. Hulina:
Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits. Inf. Control. 20(2): 114-124 (1972) - 1971
- [j6]Jon G. Bredeson, Paul T. Hulina:
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races. IEEE Trans. Computers 20(2): 225-226 (1971) - [j5]Jon G. Bredeson, Paul T. Hulina:
Generation of Prime Implicants by Direct Multiplication. IEEE Trans. Computers 20(4): 475-476 (1971) - 1970
- [j4]Paul T. Hulina, Jon G. Bredeson:
On Tracey's Internal State Assignment Method. IEEE Trans. Computers 19(5): 458 (1970) - [c1]Jon G. Bredeson, Paul T. Hulina:
Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits. SWAT 1970: 104-108
1960 – 1969
- 1969
- [j3]S. Louis Hakimi, Jon G. Bredeson:
Ternary graph theoretic error-correcting codes (Corresp.). IEEE Trans. Inf. Theory 15(3): 435-436 (1969) - 1968
- [j2]Seifollah Louis Hakimi, Jon G. Bredeson:
Graph theoretic error-correcting codes. IEEE Trans. Inf. Theory 14(4): 584-591 (1968) - 1967
- [j1]Jon G. Bredeson, Seifollah Louis Hakimi:
Decoding of graph theoretic codes (Corresp.). IEEE Trans. Inf. Theory 13(2): 348-349 (1967)
Coauthor Index
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