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Osamu Nomura
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2020 – today
- 2024
- [c10]Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie:
Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory. IJCNN 2024: 1-8 - [c9]Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie:
A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information. IJCNN 2024: 1-8 - [c8]Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie:
CMOS digital-analog mixed signal VLSI implementation of a hippocampus-inspired model. IJCNN 2024: 1-8 - [c7]Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh:
Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers. ISCAS 2024: 1-5 - 2023
- [c6]Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie:
Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors. IJCNN 2023: 1-6 - [c5]Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh:
FPGA Implementation of a Chaotic Boltzmann Machine Annealer. IJCNN 2023: 1-8 - 2022
- [j4]Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie:
Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3640-3644 (2022) - [j3]Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh:
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18(5): 3055-3065 (2022)
2000 – 2009
- 2007
- [c4]Osamu Nomura, Takashi Morie:
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) 2007: 1081-1090 - 2006
- [j2]Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. 89-C(6): 781-791 (2006) - 2005
- [c3]Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014 - 2004
- [j1]Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. 15(3-4): 173-179 (2004) - [c2]Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001 - 2003
- [c1]Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176
Coauthor Index
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