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Yeong-Kang Lai
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2020 – today
- 2024
- [c51]Yeong-Kang Lai, Ling-Cheng Huang:
An Efficient Convolutional Neural Network Accelerator on FPGA Platform. ICCE 2024: 1-2 - 2023
- [c50]Yeong-Kang Lai, Zheng-Xun Yeh:
An Efficient Convolutional Neural Network Accelerator. ICCE-Taiwan 2023: 99-100 - [c49]Yeong-Kang Lai, Yao-Hsien Huang, Yeong-Lin Lai:
Color Interpolation with Full Resolution for Hybrid RGB-IR CMOS Sensor. ICCE 2023: 1-2 - 2022
- [c48]Yeong-Kang Lai, Chuan-Wei Huang:
Object Detection Inference System with Deep Learning NVDLA Accelerator. ICCE-TW 2022: 67-68 - [c47]Yeong-Kang Lai, Yu-Jen Tsai:
Efficient Convolutional Neural Network Accelerator Based on Systolic Array. ICCE 2022: 1-2 - 2021
- [c46]Yeong-Kang Lai, Chuan-Wei Huang:
Hardware Generator for Edge Artificial Intelligent Inference System. ICCE-TW 2021: 1-2 - 2020
- [c45]Yi-Xian Kuo, Yeong-Kang Lai:
An Efficient Accelerator for Deep Convolutional Neural Networks. ICCE-TW 2020: 1-2 - [c44]Yeong-Kang Lai, Yu-Hao Hwang:
FPGA-Based Depth Separable Convolution Neural Network. ICCE 2020: 1-2 - [c43]Cheng-Hsien Chen, Yeong-Kang Lai:
The Influence Measures of Light Intensity on Machine Learning for Semantic Segmentation. ISOCC 2020: 199-200
2010 – 2019
- 2019
- [c42]Yeong-Kang Lai, Lee-Sheng Lien:
Fast Motion Estimation Based on Diamond Refinement Search for High Efficiency Video Coding. ICCE 2019: 1-2 - [c41]Yeong-Kang Lai, Shu-Ming Lee:
Locally Adaptive Contrast Enhancement Using a Modified 2D Smooth Histogram. ICCE 2019: 1-2 - 2018
- [c40]Yeong-Kang Lai, Chu-Ying Ho, Yu-Hau Huang, Chuan-Wei Huang, Yi-Xian Kuo, Yu-Chieh Chung:
Intelligent Vehicle Collision-Avoidance System with Deep Learning. APCCAS 2018: 123-126 - 2017
- [c39]Yeong-Kang Lai, Yu-Hsi Chou, Thomas Schumann:
Vehicle detection for forward collision warning system based on a cascade classifier using adaboost algorithm. ICCE-Berlin 2017: 47-48 - 2016
- [c38]Yeong-Kang Lai, Shu-Ming Lee, Jian-Wen Li, Thomas Schumann:
Dynamic gamma correction algorithm using content-based analysis for display systems. ICCE 2016: 233-234 - [c37]Yeong-Kang Lai, Yao-Hsien Huang, Chih-Ming Hwang:
Front moving object detection for car collision avoidance applications. ICCE 2016: 367-368 - [c36]Yeong-Kang Lai, Yu-Chieh Chung:
Cost-effective raster operation with enhanced shared-edge sampling for 3D graphics gaming applications. ICCE 2016: 427-428 - [c35]Yeong-Kang Lai, Chu-Yin Ho, Benjamin Freiling, Thomas Schumann:
Block based depth map estimation algorithm for 2D-to-3D conversion on FPGA. ISCAS 2016: 622-625 - [c34]Yeong-Kang Lai, Yu-Chieh Chung:
Scalable rasterizer architecture for 3D graphics system. ISCAS 2016: 1574-1577 - 2015
- [c33]Yeong-Kang Lai, Chiu-Ying Ho, Jian-Wen Li, Thomas Schumann:
Distance estimation based on disparity analysis for vehicle applications. ICCE-TW 2015: 116-117 - [c32]Yu-Chieh Chung, Yeong-Kang Lai:
A shape-perceived object tracking algorithm for intelligent surveillance systems. ICCE-TW 2015: 394-395 - [c31]Yeong-Kang Lai, Yu-Chieh Chung:
An efficient and high quality rasterization algorithm and architecture in 3D graphics systems. ISCAS 2015: 2537-2540 - 2014
- [j9]Yeong-Kang Lai, Yeong-Lin Lai, Thomas Schumann:
Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications. VLSI Design 2014: 761215:1-761215:2 (2014) - [c30]Yeong-Kang Lai, Yu-Chieh Chung, Jian-Wen Li, Chih-Ming Hwang:
Depth rendering for vehicle collision avoidance applications. ICCE-TW 2014: 73-74 - [c29]Yeong-Kang Lai, Yu-Chieh Chung:
Real-time 3D rendering processor for 2D-to-3D conversion of stereoscopic displays. ICCE 2014: 117-118 - 2013
- [j8]Yeong-Kang Lai, Yu-Chieh Chung:
3-D graphics processor unit with cost-effective rasterization using valid screen space region. IEEE Trans. Consumer Electron. 59(3): 705-713 (2013) - [c28]Yeong-Kang Lai, Yu-Chieh Chung:
Cost-effective rasterization using valid screen space region. ICCE 2013: 139-140 - [c27]Yeong-Kang Lai, Yu-Fan Lai, Cheng-Han Dai, Thomas Schumann:
Perceptual video quality assessment for wireless multimedia applications. ICCE 2013: 496-497 - [c26]Yeong-Kang Lai, Yu-Chieh Chung, Yu-Fan Lai:
Hardware implementation for real-time 3D rendering in 2D-to-3D conversion. ISCAS 2013: 893-896 - [c25]Benjamin Freiling, Thomas Schumann, Yeong-Kang Lai, Yu-Fan Lai:
Block based depth map estimation algorithm for 2D-to-3D conversion. ISCE 2013: 53-54 - 2012
- [c24]Yeong-Kang Lai, Yen-Fang Lai, Yu-Fan Lai:
Algorithm and architecture design of sorting-based motion estimation algorithm for wireless video applications. ICCE 2012: 199-200 - [c23]Yeong-Kang Lai, Yu-Fan Lai, Ying-Chang Chen:
An effective hybrid depth-perception algorithm for 2D-to-3D conversion in 3D display systems. ICCE 2012: 612-613 - [c22]Yeong-Kang Lai, Shu-Ming Lee, Yu-Fan Lai:
Wide color-gamut improvement with skin protection using content-based analysis for display systems. ICCE 2012: 638-639 - [c21]Yeong-Kang Lai, Yu-Fan Lai, Jung-Wei Lin:
High-quality view synthesis algorithm and architecture for 2D to 3D conversion. ISCAS 2012: 373-376 - 2011
- [c20]Yeong-Kang Lai, Yu-Fan Lai, Cheng-Han Dai:
A novel perceptual video coding algorithm and architecture design for H.264/AVC. ICME 2011: 1-6 - 2010
- [j7]Yeong-Kang Lai, Lien-Fei Chen, Shien-Yu Huang:
Hybrid parallel motion estimation architecture based on fast top-winners search algorithm. IEEE Trans. Consumer Electron. 56(3): 1837-1842 (2010) - [j6]Yeong-Kang Lai, Yu-Fan Lai:
A reconfigurable IDCT architecture for universal video decoders. IEEE Trans. Consumer Electron. 56(3): 1872-1879 (2010) - [j5]Yeong-Kang Lai, Lien-Fei Chen, Wei-Che Chiou:
A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC. IEEE Trans. Consumer Electron. 56(4): 2812-2818 (2010)
2000 – 2009
- 2009
- [j4]Yeong-Kang Lai, Lien-Fei Chen, Yui-Chih Shih:
A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform. IEEE Trans. Consumer Electron. 55(2): 400-407 (2009) - [c19]Lien-Fei Chen, Shin-Ping Yang, Yeong-Kang Lai:
Model-based early termination scheme for H.264/AVC inter prediction. ICASSP 2009: 597-600 - [c18]Lien-Fei Chen, Shien-Yu Huang, Chi-Yao Liao, Yeong-Kang Lai:
Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation. ISCAS 2009: 1657-1660 - 2008
- [c17]Lien-Fei Chen, Kun-Hsing Li, Chong-Yu Huang, Yeong-Kang Lai:
Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder. ICME 2008: 145-148 - [c16]Yeong-Kang Lai, Lien-Fei Chen, Tian-En Hsieh, Shien-Yu Huang:
Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm. ICME 2008: 1021-1024 - [c15]Chong-Yu Huang, Lien-Fei Chen, Yeong-Kang Lai:
A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. ISCAS 2008: 21-24 - 2006
- [j3]Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu:
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications. IEICE Trans. Electron. 89-C(11): 1674-1675 (2006) - [c14]Lien-Fei Chen, Tai-Lun Huang, Tzau-Min Chou, Yeong-Kang Lai:
Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000. ICASSP (3) 2006: 964-967 - 2005
- [c13]Lien-Fei Chen, Tai-Lun Huang, Yeong-Kang Lai:
Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications. ICASSP (5) 2005: 17-20 - [c12]Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung:
A simple and cost effective video encoder with memory-reducing CAVLC. ISCAS (1) 2005: 432-435 - [c11]Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu:
A two-way SIMD-based reconfigurable computing architecture for multimedia applications. ISCAS (5) 2005: 4578-4581 - 2004
- [c10]Yeong-Kang Lai, Lien-Fei Chen:
A performance-driven configurable motion estimator for full-search block-matching algorithm. ISCAS (2) 2004: 233-236 - [c9]Yeong-Kang Lai, Li-Chung Chang, Lien-Fei Chen, Chih-Chung Chou, Chun-Wei Chiu:
A novel memoryless AES cipher architecture for networking applications. ISCAS (4) 2004: 333-336 - [c8]Lien-Fei Chen, Yeong-Kang Lai:
VLSI architecture of the reconfigurable computing engine for digital signal processing applications. ISCAS (2) 2004: 937-940 - 2003
- [c7]Yeong-Kang Lai, Han-Jen Hsu:
A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath. ISCAS (2) 2003: 492-495 - [c6]Yeong-Kang Lai, Lien-Fei Chen:
A high data-reuse architecture with double-slice processing for full-search block-matching algorithm. ISCAS (2) 2003: 716-719 - 2001
- [j2]Yeong-Kang Lai:
A memory efficient motion estimator for three step search block-matching algorithm. IEEE Trans. Consumer Electron. 47(3): 644-651 (2001) - [c5]Yeong-Kang Lai, Yu-Chuan Shu:
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. ISCAS (4) 2001: 57-60 - 2000
- [c4]Yeong-Kang Lai, Kuo-Chen Chen:
A novel VLSI architecture for Lempel-Ziv based data compression. ISCAS 2000: 617-620
1990 – 1999
- 1998
- [j1]Yeong-Kang Lai, Liang-Gee Chen:
A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm. IEEE Trans. Circuits Syst. Video Technol. 8(2): 124-127 (1998) - 1997
- [c3]Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee:
A flexible data-interlacing architecture for full-search block-matching algorithm. ASAP 1997: 96- - [c2]Yeong-Kang Lai, Liang-Gee Chen, Tsung-Han Tsai, Po-Cheng Wu:
A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation. ICIP (2) 1997: 144-147 - 1996
- [c1]Po-Cheng Wu, Liang-Gee Chen, Yeong-Kang Lai, Tsung-Han Tsai:
Design strategy for three-dimensional subband filter banks. ICIP (1) 1996: 605-608
Coauthor Index
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