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Jae-Yun Park

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2024
[j2]
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Jae-Yun Park, Jae-Won Nam:
A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4663-4667 (2024)
2023
[j1]
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Jae-Yun Park, Su-Hyeon Kim, Hyunyoung Yoo, Jae-Won Nam:
Analysis of Quarter Method Applied ROM-Based DDFS Architecture. IEEE Access 11: 117137-117148 (2023)

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