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Journal Articles
- 2023
[j4]Saleh Abdel-Hafeez
, Shadi M. Harb:
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems. IET Comput. Digit. Tech. 17(3-4): 141-148 (2023)- 2015
- [j3]Shadi M. Harb, Issa Batarseh, Ahmad Harb:
Development, Implementation, Assessment of a Web-based Circuit Solver for Teaching Basic Electrical Circuits Theory. Int. J. Online Eng. 11(4): 55-61 (2015) - 2011
- [j2]Saleh Abdel-Hafeez, Ann Gordon-Ross, Asem Albosul, Ahmad Shatnawi, Shadi M. Harb:
A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter. Informatica (Slovenia) 35(2): 211-219 (2011) - 2006
- [j1]Saleh Abdel-Hafeez, Shadi M. Harb:
A VLSI High-Performance Priority Encoder Using Standard CMOS Library. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 597-601 (2006)
Conference and Workshop Papers
- 2021
- [c10]Shadi M. Harb, William R. Eisenstadt:
Signal Integrity in High Speed 3D IC Design- A Case Study. NorCAS 2021: 1-5 - 2017
- [c9]Shadi M. Harb, William R. Eisenstadt:
A study of characterizing crosstalk effects in 3-D vias. LASCAS 2017: 1-4 - 2016
- [c8]Shadi M. Harb, William R. Eisenstadt:
Oscillation ring testing methodology of TSVs in 3D stacked ICs. NORCAS 2016: 1-4 - 2015
- [c7]Shadi M. Harb, William R. Eisenstadt:
A CMOS High Resolution Multi-Edge Delay Generator. NORCAS 2015: 1-4 - 2011
- [c6]Shadi M. Harb, William R. Eisenstadt, Robert M. Fox:
A sub-1V CMOS voltage reference generator. ISCAS 2011: 901-904 - 2009
- [c5]Moishe Groger, Shadi M. Harb, Devin Morris, William R. Eisenstadt, Sudeep Puligundla:
High speed I/O and thermal effect characterization of 3D stacked ICs. 3DIC 2009: 1-5 - 2008
- [c4]Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt:
High speed digital CMOS divide-by-N fequency divider. ISCAS 2008: 592-595 - [c3]Shadi M. Harb, Janise McNair:
Analytical Study of the Expected Number of Hops in Wireless Ad Hoc Network. WASA 2008: 63-71 - 2007
- [c2]Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt:
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. PATMOS 2007: 75-85 - [c1]Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt:
A low-power CAM using a 12-transistor design cell. VLSI-SoC 2007: 264-269
Coauthor Index
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