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2010 – 2019
- 2016
[j1]Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang:
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC. IEEE Des. Test 33(1): 59-67 (2016)- 2015
- [c4]Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang:
Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. ITC 2015: 1-10 - 2013
- [c3]Bruce Querbach, Sudeep Puligundla, Daniel Becerra, Zale T. Schoenborn, Patrick Chiang:
Comparison of hardware based and software based stress testing of memory IO interface. MWSCAS 2013: 637-640 - 2010
- [c2]Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran:
Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. ITC 2010: 405-409
2000 – 2009
- 2009
- [c1]Moishe Groger, Shadi M. Harb, Devin Morris, William R. Eisenstadt
, Sudeep Puligundla:
High speed I/O and thermal effect characterization of 3D stacked ICs. 3DIC 2009: 1-5
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