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ORCIDHojin Kee
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2010 – 2019
- 2017
[j3]Swapnil Mhaske
, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. Int. J. Reconfigurable Comput. 2017: 3689308:1-3689308:23 (2017)- 2016
- [c9]Swapnil Mhaske, Hojin Kee, Tai Ly, Predrag Spasojevic:
FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis. Sarnoff Symposium 2016: 19-21 - 2015
- [c8]Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. Sarnoff Symposium 2015: 88-93 - [c7]Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
High-Throughput FPGA-Based QC-LDPC Decoder Architecture. VTC Fall 2015: 1-5 - [i2]Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
High-Throughput FPGA-based QC-LDPC Decoder Architecture. CoRR abs/1503.02986 (2015) - [i1]Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R. CoRR abs/1505.04339 (2015) - 2014
- [c6]Hojin Kee, Swapnil Mhaske, David Uliana, Adam Arnesen, Newton Petersen, Taylor L. Riché, Dustyn Blasig, Tai Ly:
Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. GlobalSIP 2014: 45-49 - 2012
- [j2]Hojin Kee, Chung-Ching Shen, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao, Jacob Kornerup:
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware. J. Signal Process. Syst. 66(3): 285-301 (2012) - 2011
- [j1]Nimish Sane, Hojin Kee, Gunasekaran S. Seetharaman, Shuvra S. Bhattacharyya:
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs. J. Signal Process. Syst. 65(2): 229-244 (2011) - 2010
- [b1]Hojin Kee:
Systematic Exploration of Trade-Offs between Application Throughput and Hardware Resource Requirements in DSP Systems. University of Maryland, College Park, MD, USA, 2010 - [c5]Hojin Kee, Shuvra S. Bhattacharyya, Ian C. Wong, Yong Rao:
FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques. ICASSP 2010: 1510-1513 - [c4]Hsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya:
Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs. International Symposium on Rapid System Prototyping 2010: 1-7 - [c3]Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup:
Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs. ICSAMOS 2010: 136-143
2000 – 2009
- 2009
- [c2]Hojin Kee, Shuvra S. Bhattacharyya, Newton Petersen, Jacob Kornerup:
Resource-efficient acceleration of 2-dimensional Fast Fourier Transform computations on FPGAs. ICDSC 2009: 1-8 - 2008
- [c1]Hojin Kee, Newton Petersen, Jacob Kornerup, Shuvra S. Bhattacharyya:
Systematic generation of FPGA-based FFT implementations. ICASSP 2008: 1413-1416
Coauthor Index
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